From patchwork Wed Aug 21 13:49:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 2847746 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 29AAC9F271 for ; Wed, 21 Aug 2013 13:50:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E8A2320514 for ; Wed, 21 Aug 2013 13:50:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9356220512 for ; Wed, 21 Aug 2013 13:50:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751725Ab3HUNuC (ORCPT ); Wed, 21 Aug 2013 09:50:02 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:44117 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751556Ab3HUNuA (ORCPT ); Wed, 21 Aug 2013 09:50:00 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRV000U6VQZRHK0@mailout3.samsung.com> for linux-mmc@vger.kernel.org; Wed, 21 Aug 2013 22:49:59 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.47]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 2E.3C.29708.785C4125; Wed, 21 Aug 2013 22:49:59 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-11-5214c587820c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 56.A1.31505.785C4125; Wed, 21 Aug 2013 22:49:59 +0900 (KST) Received: from DOTGIHJUN01 ([12.23.118.161]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRV00053VRBW640@mmp2.samsung.com>; Wed, 21 Aug 2013 22:49:59 +0900 (KST) From: Seungwon Jeon To: linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Jaehoon Chung' , 'Alim Akhtar' References: In-reply-to: Subject: [PATCH 03/14] mmc: dw_mmc: exynos: adjust the clock rate with speed mode Date: Wed, 21 Aug 2013 22:49:59 +0900 Message-id: <002801ce9e75$53f265c0$fbd73140$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac03z3aCvVFr8FaITt2vKVQKst76fw3OcIrwS9fJ1BA= Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t8zfd32oyJBBluPm1g8mLeNzWL7641s Fjd+tbFaHPnfz+jA4nHoylpGj74tqxg9Pm+SC2CO4rJJSc3JLEst0rdL4MpYvf8se8FZyYqj K00aGBtFuxg5OSQETCQWb2hig7DFJC7cWw9kc3EICSxjlPg7+w4rTNGaaa2sEInpjBIt2x8y Qzh/GCWefjkNVsUmoCXx980bZhBbREBW4uefC2BjmQXKJN7euQ8U5wBq4JZY3RwEEuYU4JFY 96cTrFxYIFji3KWzTCA2i4CqxPbXT9lBbF4BW4mzXw6xQdiCEj8m32MBGcMsoC4xZUouxHR5 ic1r3oJNlwAKP/qrC3GAlcTh5UdYIUpEJPa9eMcIcrGEwCF2ieWzbjFCrBKQ+Db5EAtEr6zE pgPMEO9KShxccYNlAqPELCSLZyEsnoVk8SwkGxYwsqxiFE0tSC4oTkovMtErTswtLs1L10vO z93ECInCCTsY7x2wPsSYDLR9IrOUaHI+MIrzSuINjc2MLExNTI2NzC3NSBNWEudVb7EOFBJI TyxJzU5NLUgtii8qzUktPsTIxMEp1cAoIlefIXa2rbPtdYLHo1VvOmMMT9Tfc/vD59/5fTaT Y8sKiclh856dZ17G5xDgG3rPYmrPRPY7E9LO8qUeu3Dl+fYJQd9NZDyNzt9galpb5NnyXqz1 cbpb6Px1G88IZL97kTrfc4PB/k/Hjvy21NjxNyVplb3vMa6e83viQ3bK/zCs+PP8m9kzJZbi jERDLeai4kQAWwFPYtgCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEKsWRmVeSWpSXmKPExsVy+t9jQd32oyJBBrsOGVg8mLeNzWL7641s Fjd+tbFaHPnfz+jA4nHoylpGj74tqxg9Pm+SC2COamC0yUhNTEktUkjNS85PycxLt1XyDo53 jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAFap6RQlphTChQKSCwuVtK3wzQhNMRN1wKmMULX NyQIrsfIAA0krGPMWL3/LHvBWcmKoytNGhgbRbsYOTkkBEwk1kxrZYWwxSQu3FvP1sXIxSEk MJ1RomX7Q2YI5w+jxNMvp8Gq2AS0JP6+ecMMYosIyEr8/HOBDcRmFiiTeHvnPlCcA6iBW2J1 cxBImFOAR2Ldn06wcmGBYIlzl84ygdgsAqoS218/ZQexeQVsJc5+OcQGYQtK/Jh8jwVkDLOA usSUKbkQ0+UlNq95CzZdAij86K8uxAFWEoeXH2GFKBGR2PfiHeMERqFZSAbNQhg0C8mgWUg6 FjCyrGIUTS1ILihOSs810itOzC0uzUvXS87P3cQIjvFn0jsYVzVYHGIU4GBU4uG9sFMkSIg1 say4MvcQowQHs5II7+f9QCHelMTKqtSi/Pii0pzU4kOMyUBvTmSWEk3OB6afvJJ4Q2MTMyNL IzMLIxNzc9KElcR5D7ZaBwoJpCeWpGanphakFsFsYeLglGpgdCmdKHG5wNtbglNvm2t77C7/ sqUhcwQnzNQT4XtcLaPsv7IjjlXh5ePorRrPNz7a0XtB7Z/oL4nfiwMWfHyyQ65+RZLf+fxd EluiH7Cp1Lp6z4/fs3vDrPi1dm7S3YylvN02x2V0d3KZbJ3r77rDMYRtWd+mozzTlmnM2LFx NrtLoXTra7UaJZbijERDLeai4kQAFJyaqDUDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos's host has divider logic before 'cclk_in' to controller core. It means that actual clock rate of ciu clock comes from this divider value. So, source clock should be adjusted along with 'ciu_div' which indicates the host's divider ratio. Setting clock rate basically fits the required speed. Specially, 'cclk_in' should have double rate of target speed in case of DDR 8-bit mode. Signed-off-by: Seungwon Jeon --- drivers/mmc/host/dw_mmc-exynos.c | 44 ++++++++++++++++++++++++++++--------- 1 files changed, 33 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 90f9335..f16e2fc 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -49,6 +49,7 @@ struct dw_mci_exynos_priv_data { u8 ciu_div; u32 sdr_timing; u32 ddr_timing; + u32 cur_speed; }; static struct dw_mci_exynos_compatible { @@ -91,14 +92,9 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) static int dw_mci_exynos_setup_clock(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; + unsigned long rate = clk_get_rate(host->ciu_clk); - if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250) - host->bus_hz /= (priv->ciu_div + 1); - else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) - host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV; - else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) - host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV; - + host->bus_hz = rate / (priv->ciu_div + 1); return 0; } @@ -118,11 +114,31 @@ static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr) static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) { struct dw_mci_exynos_priv_data *priv = host->priv; + unsigned int wanted = ios->clock; + unsigned long actual; + u8 div = priv->ciu_div + 1; + - if (ios->timing == MMC_TIMING_UHS_DDR50) + if (ios->timing == MMC_TIMING_UHS_DDR50) { mci_writel(host, CLKSEL, priv->ddr_timing); - else + /* Should be double rate for DDR mode */ + if (ios->bus_width == MMC_BUS_WIDTH_8) + wanted <<= 1; + } else { mci_writel(host, CLKSEL, priv->sdr_timing); + } + + if (wanted && (priv->cur_speed != wanted)) { + int ret = clk_set_rate(host->ciu_clk, wanted * div); + if (ret) + dev_warn(host->dev, + "failed to set clk-rate %u error: %d\n", + wanted * div, ret); + actual = clk_get_rate(host->ciu_clk); + host->bus_hz = actual / div; + priv->cur_speed = wanted; + host->current_speed = 0; + } } static int dw_mci_exynos_parse_dt(struct dw_mci *host) @@ -133,8 +149,14 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host) u32 div = 0; int ret; - of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); - priv->ciu_div = div; + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) + priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; + else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) + priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; + else { + of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); + priv->ciu_div = div; + } ret = of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2);