From patchwork Fri Mar 7 13:30:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3791371 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CE477BF540 for ; Fri, 7 Mar 2014 13:30:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CA49B201F0 for ; Fri, 7 Mar 2014 13:30:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4987320154 for ; Fri, 7 Mar 2014 13:30:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753211AbaCGNag (ORCPT ); Fri, 7 Mar 2014 08:30:36 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:24844 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753186AbaCGNaf (ORCPT ); Fri, 7 Mar 2014 08:30:35 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N2200D4TIUZN710@mailout4.samsung.com> for linux-mmc@vger.kernel.org; Fri, 07 Mar 2014 22:30:35 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.49]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id A2.30.14803.AF9C9135; Fri, 07 Mar 2014 22:30:34 +0900 (KST) X-AuditID: cbfee691-b7efc6d0000039d3-e7-5319c9fa990f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 8F.5C.28157.AF9C9135; Fri, 07 Mar 2014 22:30:34 +0900 (KST) Received: from DOTGIHJUN01 ([12.36.185.168]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N220037MIUYVH50@mmp2.samsung.com>; Fri, 07 Mar 2014 22:30:34 +0900 (KST) From: Seungwon Jeon To: linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Ulf Hansson' References: <1383653403-10049-1-git-send-email-ulf.hansson@linaro.org> <006001cf2a57$73a07290$5ae157b0$%jun@samsung.com> In-reply-to: <006001cf2a57$73a07290$5ae157b0$%jun@samsung.com> Subject: [PATCH v3 1/7] mmc: clarify DDR timing mode between SD-UHS and eMMC Date: Fri, 07 Mar 2014 22:30:34 +0900 Message-id: <002901cf3a09$6b6520a0$422f61e0$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac7aH/uUm1J6MxFOSyaXb4Fx/nx/rAABnFmgDfJZ22AGGVY+QAPsoLRA Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRmVeSWpSXmKPExsVy+t8zQ91fJyWDDaY22FpMuLyd0eLI/35G i+Nrwx2YPe5c28PmcePVQiaPz5vkApijuGxSUnMyy1KL9O0SuDLaXk1hLrjDW3H53yf2Bsa1 3F2MnBwSAiYSR859ZIGwxSQu3FvP1sXIxSEksIxR4nXTJhaYopsnW5ggEtMZJVomLGAHSQgJ /GGU2LpXGMRmE9CS+PvmDTOILSIgK/HzzwU2EJtZwFvizOcpzBD1VRLz7p4C6+UUsJPYc2kd 2AJhAR+JZ/efgNWzCKhKbJl/DqyGV8BWYt3fLUwQtqDEj8n3gOo5gGaqS0yZkgsxXl5i85q3 zCBhCaDwo7+6EBe4SUy49YUJokREYt+Ld4wg50sI7GOX+DtxDTvEKgGJb5MPsUD0ykpsOsAM 8a6kxMEVN1gmMErMQrJ4FsLiWUgWz0KyYQEjyypG0dSC5ILipPQiU73ixNzi0rx0veT83E2M kNibuIPx/gHrQ4zJQNsnMkuJJucDYzevJN7Q2MzIwtTE1NjI3NKMNGElcd70R0lBQgLpiSWp 2ampBalF8UWlOanFhxiZODilGhiZGnf7n7dMOnnAYELyf4ago4+L7ZRTrl9f4T7lX7jakrR5 ofWvo7rvu3ktro6atq1NZsGetRszJUX23P8ySVH4a+xXqW8/BNY/2NkU4RFiutpb75nRu8pP 1Vxhtk6HnB2ORIcotzZmxf7/Kn23p8X68kOJSRbv5KomKPOtLKg3nMHtGJPKL6DEUpyRaKjF XFScCAAsfWQc0wIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLKsWRmVeSWpSXmKPExsVy+t9jQd1fJyWDDaYus7SYcHk7o8WR//2M FsfXhjswe9y5tofN48arhUwenzfJBTBHNTDaZKQmpqQWKaTmJeenZOal2yp5B8c7x5uaGRjq GlpamCsp5CXmptoqufgE6Lpl5gAtUlIoS8wpBQoFJBYXK+nbYZoQGuKmawHTGKHrGxIE12Nk gAYS1jFmtL2awlxwh7fi8r9P7A2Ma7m7GDk5JARMJG6ebGGCsMUkLtxbz9bFyMUhJDCdUaJl wgJ2kISQwB9Gia17hUFsNgEtib9v3jCD2CICshI//1xgA7GZBbwlznyewgxRXyUx7+4psF5O ATuJPZfWsYDYwgI+Es/uPwGrZxFQldgy/xxYDa+ArcS6v1uYIGxBiR+T7wHVcwDNVJeYMiUX Yry8xOY1b5lBwhJA4Ud/dSEucJOYcOsLE0SJiMS+F+8YJzAKzUIyaBbCoFlIBs1C0rGAkWUV o2hqQXJBcVJ6rpFecWJucWleul5yfu4mRnBkP5PewbiqweIQowAHoxIPb8ciiWAh1sSy4src Q4wSHMxKIrw8qyWDhXhTEiurUovy44tKc1KLDzEmA705kVlKNDkfmHTySuINjU3MjCyNzCyM TMzNSRNWEuc92GodKCSQnliSmp2aWpBaBLOFiYNTqoHR89Q8K0euyLr/Nkcfi7Avbj5Vucww 4b6yeOKHbI9nf26tSJqYsrT4XnlL1+mNnBbWXDFlzHNNg4PXvJrE+2q7kMDXWUrbW2s35iZF P/nMuD7x1TLhQ7Vds55q7znudZfFa3NJxyW3o5t3TkibdH6idrzu7+JZCVY/XlaKiz1NMlPb /vRpnN83JZbijERDLeai4kQAvfPF4zADAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change distinguishes DDR timing mode of current mixed usage to clarify device type. Signed-off-by: Seungwon Jeon Acked-by: Ulf Hansson Acked-by: Jaehoon Chung --- drivers/mmc/core/debugfs.c | 3 +++ drivers/mmc/core/mmc.c | 2 +- include/linux/mmc/host.h | 3 ++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c index 54829c0..509229b 100644 --- a/drivers/mmc/core/debugfs.c +++ b/drivers/mmc/core/debugfs.c @@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data) case MMC_TIMING_UHS_DDR50: str = "sd uhs DDR50"; break; + case MMC_TIMING_MMC_DDR52: + str = "mmc DDR52"; + break; case MMC_TIMING_MMC_HS200: str = "mmc high-speed SDR200"; break; diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 1ab5f3a..e22d851 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1264,7 +1264,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, goto err; } mmc_card_set_ddr_mode(card); - mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50); + mmc_set_timing(card->host, MMC_TIMING_MMC_DDR52); mmc_set_bus_width(card->host, bus_width); } } diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index cb61ea4..3535420 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -58,7 +58,8 @@ struct mmc_ios { #define MMC_TIMING_UHS_SDR50 5 #define MMC_TIMING_UHS_SDR104 6 #define MMC_TIMING_UHS_DDR50 7 -#define MMC_TIMING_MMC_HS200 8 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 #define MMC_SDR_MODE 0 #define MMC_1_2V_DDR_MODE 1