From patchwork Fri Mar 14 12:12:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3832501 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AF7CF9F2BB for ; Fri, 14 Mar 2014 12:12:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC4BE20320 for ; Fri, 14 Mar 2014 12:12:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DC3A420306 for ; Fri, 14 Mar 2014 12:12:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754382AbaCNMMq (ORCPT ); Fri, 14 Mar 2014 08:12:46 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:44456 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754367AbaCNMMo (ORCPT ); Fri, 14 Mar 2014 08:12:44 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N2F009B6DX7NK10@mailout2.samsung.com> for linux-mmc@vger.kernel.org; Fri, 14 Mar 2014 21:12:43 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.51]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id F2.81.10092.B32F2235; Fri, 14 Mar 2014 21:12:43 +0900 (KST) X-AuditID: cbfee68f-b7f156d00000276c-ea-5322f23bb526 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 01.EF.29263.B32F2235; Fri, 14 Mar 2014 21:12:43 +0900 (KST) Received: from DOTGIHJUN01 ([12.36.185.168]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N2F00JEADX7W760@mmp2.samsung.com>; Fri, 14 Mar 2014 21:12:43 +0900 (KST) From: Seungwon Jeon To: linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Jaehoon Chung' References: <1383653403-10049-1-git-send-email-ulf.hansson@linaro.org> <006501cf2a57$881b0ff0$98512fd0$%jun@samsung.com> In-reply-to: Subject: [PATCH RESEMD v3 6/7] mmc: dw_mmc: clarify DDR timing mode between SD-UHS and eMMC Date: Fri, 14 Mar 2014 21:12:43 +0900 Message-id: <003801cf3f7e$b3c7f910$1b57eb30$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac7aH/uUm1J6MxFOSyaXb4Fx/nx/rAABnFmgDfJZ22AGGaDjEAPssJ/wAVyNHUA= Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEIsWRmVeSWpSXmKPExsVy+t8zY13rT0rBBi8PSllMuLyd0eLGrzZW iyP/+xkdmD1uvFrI5NG3ZRWjx+dNcgHMUVw2Kak5mWWpRfp2CVwZR1oXsBX85Ks4Nm8rUwPj Pp4uRk4OCQETiZNrl7NB2GISF+6tB7OFBJYxSuxZYAhT86fjAnMXIxdQfDqjxMcD7xkhiv4w SsxbaQBiswloSfx984YZxBYRkJX4+ecC2CBmAV+JBd+nM0HUV0lcujUNrJdTgEdi3Z9OsHph gViJg59XgtWzCKhK9NxcywJi8wrYSlzsvskIYQtK/Jh8jwViprrEpHmLmCFseYnNa94C2RxA h6pLPPqrC3GCn8SqJfOgSkQk9r14xwhyv4TAPnaJA+samSB2CUh8m3yIBaJXVmLTAWaIfyUl Dq64wTKBUWIWks2zkGyehWTzLCQrFjCyrGIUTS1ILihOSi8y1itOzC0uzUvXS87P3cQIib/+ HYx3D1gfYkwGWj+RWUo0OR8Yv3kl8YbGZkYWpiamxkbmlmakCSuJ895/mBQkJJCeWJKanZpa kFoUX1Sak1p8iJGJg1OqgXHNtqopgV//OT3KmNL917xVmqtYdGLb4mhljQPdzI/UZst6RKv8 m2bwYcftDyVR7//uiyk73KCfP1cgLyl642y50O39ayKEdHdzvX64SvNPUsntyc9eMZ9/f2iR uMaxi9PtPctVvzxiXXew8c2cdfMK4kVP1vVcCZq9cWXZtn/hGivKxKV2Pj+vxFKckWioxVxU nAgAJ4tWmNUCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAKsWRmVeSWpSXmKPExsVy+t9jQV3rT0rBBgsbxS0mXN7OaHHjVxur xZH//YwOzB43Xi1k8ujbsorR4/MmuQDmqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwND XUNLC3MlhbzE3FRbJRefAF23zBygTUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqM DNBAwjrGjCOtC9gKfvJVHJu3lamBcR9PFyMnh4SAicSfjgvMELaYxIV769m6GLk4hASmM0p8 PPCeESQhJPCHUWLeSgMQm01AS+LvmzdgDSICshI//1xgA7GZBXwlFnyfzgRRXyVx6dY0sF5O AR6JdX86weqFBWIlDn5eCVbPIqAq0XNzLQuIzStgK3Gx+yYjhC0o8WPyPRaImeoSk+YtYoaw 5SU2r3kLZHMAHaou8eivLsQJfhKrlsyDKhGR2PfiHeMERqFZSCbNQjJpFpJJs5C0LGBkWcUo mlqQXFCclJ5rqFecmFtcmpeul5yfu4kRHN/PpHYwrmywOMQowMGoxMPrcFgxWIg1say4MvcQ owQHs5II78nHSsFCvCmJlVWpRfnxRaU5qcWHGJOBHp3ILCWanA9MPXkl8YbGJmZGlkZmFkYm 5uakCSuJ8x5otQ4UEkhPLEnNTk0tSC2C2cLEwSnVwDhnb96fyavUfR0STjLH6/tpX5gtYCNw plT7gulvz+VL7Hc02pkeSXE+l6dRK70mqTsnaLfBlEVSywVmF7EwKssuvFxXE738s43PlSvy vnO33OGUMF8ervAmdkVVQc1VuaQ36VMbbm35artexNr6jNb5+c+P3p5uxfu0yj6AeZlT2/SZ /fP6FiixFGckGmoxFxUnAgD+9xZeMwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Replaced UHS_DDR50 with MMC_DDR52. And MMC_CAP_UHS_DDR50 is removed because of non-implementation of UHS signaling. Signed-off-by: Seungwon Jeon Reviewed-by: Ulf Hansson Acked-by: Jaehoon Chung --- drivers/mmc/host/dw_mmc-exynos.c | 5 ++--- drivers/mmc/host/dw_mmc.c | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 3423c5e..a67e784 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -187,7 +187,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) unsigned long actual; u8 div = priv->ciu_div + 1; - if (ios->timing == MMC_TIMING_UHS_DDR50) { + if (ios->timing == MMC_TIMING_MMC_DDR52) { mci_writel(host, CLKSEL, priv->ddr_timing); /* Should be double rate for DDR mode */ if (ios->bus_width == MMC_BUS_WIDTH_8) @@ -386,8 +386,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode, /* Common capabilities of Exynos4/Exynos5 SoC */ static unsigned long exynos_dwmmc_caps[4] = { - MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, + MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, MMC_CAP_CMD23, MMC_CAP_CMD23, MMC_CAP_CMD23, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 0c56faa..ab704d9 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -962,7 +962,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) regs = mci_readl(slot->host, UHS_REG); /* DDR mode set */ - if (ios->timing == MMC_TIMING_UHS_DDR50) + if (ios->timing == MMC_TIMING_MMC_DDR52) regs |= ((0x1 << slot->id) << 16); else regs &= ~((0x1 << slot->id) << 16);