diff mbox

[v2,1/2] mmc/host/rtsx: Configure SD_CFG2 register in sd_rw_multi

Message ID 00fb063304a0720f3ba9db6f79bb67263d450356.1353377266.git.wei_wang@realsil.com.cn (mailing list archive)
State New, archived
Headers show

Commit Message

wei_wang@realsil.com.cn Nov. 20, 2012, 2:09 a.m. UTC 
From: Wei WANG <wei_wang@realsil.com.cn>

For Realtek card reader, internal regsiter SD_CFG2 should be configured
before transferring data. In the prior version, the value of this register
has been calculated, but forgotten to write back to the internal register.

Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
---
 drivers/mmc/host/rtsx_pci_sdmmc.c |    1 +
 1 file changed, 1 insertion(+)

Comments

Chris Ball Nov. 20, 2012, 2:21 a.m. UTC | #1 
Hi,

Sorry to be pedantic, but:

On Mon, Nov 19 2012, wei_wang@realsil.com.cn wrote:
> For Realtek card reader, internal regsiter SD_CFG2 should be configured
> before transferring data. In the prior version, the value of this register
> has been calculated, but forgotten to write back to the internal register.

With what consequences?  Was the  data transfer failing?  Under which
circumstances?

Thanks,

- Chris.
wei_wang@realsil.com.cn Nov. 20, 2012, 2:40 a.m. UTC | #2 
? 2012?11?20? 10:21, Chris Ball ??:
> Hi,
>
> Sorry to be pedantic, but:
>
> On Mon, Nov 19 2012, wei_wang@realsil.com.cn wrote:
>> For Realtek card reader, internal regsiter SD_CFG2 should be configured
>> before transferring data. In the prior version, the value of this register
>> has been calculated, but forgotten to write back to the internal register.
> With what consequences?  Was the  data transfer failing?  Under which
> circumstances?
>
> Thanks,
>
> - Chris.

Hi Chris:

It's about compatibility issue. The default value of SD_CFG2 is proper 
for writing data. But for reading sequence, the timing is not good 
enough. So in some extreme circumstance,  card reader may sample the 
response data from the card as good even if the data is wrong. And this 
will cause the bad consequence.

Shall I modify the commit and resend the patchset again?

BR,
Wei WANG
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Chris Ball Nov. 20, 2012, 3:09 a.m. UTC | #3 
Hi,

On Mon, Nov 19 2012, wwang wrote:
> It's about compatibility issue. The default value of SD_CFG2 is proper
> for writing data. But for reading sequence, the timing is not good
> enough. So in some extreme circumstance,  card reader may sample the
> response data from the card as good even if the data is wrong. And
> this will cause the bad consequence.
>
> Shall I modify the commit and resend the patchset again?

Thanks!  Yes, please resend.

I won't be merging this one because Samuel is merging the initial
patchset, but I'll merge patches for the MMC side after 3.8.  For these:

Acked-by: Chris Ball <cjb@laptop.org>

- Chris.
diff mbox

Patch

diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c
index 0e934bf..067dd46 100644
--- a/drivers/mmc/host/rtsx_pci_sdmmc.c
+++ b/drivers/mmc/host/rtsx_pci_sdmmc.c
@@ -405,6 +405,7 @@  static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 			0x01, RING_BUFFER);
 
+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 			trans_mode | SD_TRANSFER_START);
 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,