From patchwork Fri Nov 26 23:02:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 360132 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oAQN1Sqa004705 for ; Fri, 26 Nov 2010 23:03:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753124Ab0KZXDL (ORCPT ); Fri, 26 Nov 2010 18:03:11 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:42881 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751684Ab0KZXDJ (ORCPT ); Fri, 26 Nov 2010 18:03:09 -0500 Received: from yukiko.kent.sydney.vergenet.net (219-109-213-121.bitcat.net [219.109.213.121]) by kirsty.vergenet.net (Postfix) with ESMTP id 7C78B245A5; Sat, 27 Nov 2010 10:03:06 +1100 (EST) Received: by yukiko.kent.sydney.vergenet.net (Postfix, from userid 7100) id 7A34EC3072; Sat, 27 Nov 2010 08:03:05 +0900 (JST) From: Simon Horman To: linux-mmc@vger.kernel.org, linux-sh@vger.kernel.org Cc: Yusuke Goda , Magnus Damm , Kuninori Morimoto , Chris Ball , Paul Mundt , Simon Horman Subject: [PATCH 3/3] sh, mmc: Use defines when setting CE_CLK_CTRL Date: Sat, 27 Nov 2010 08:02:59 +0900 Message-Id: <1290812579-20410-3-git-send-email-horms@verge.net.au> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1290812579-20410-1-git-send-email-horms@verge.net.au> References: <1290812579-20410-1-git-send-email-horms@verge.net.au> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 26 Nov 2010 23:03:12 +0000 (UTC) diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h index 519a2cd..adf9dba 100644 --- a/include/linux/mmc/sh_mmcif.h +++ b/include/linux/mmc/sh_mmcif.h @@ -77,6 +77,9 @@ struct sh_mmcif_plat_data { #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) +#define CLKDIV_4 (1<<16) /* mmc clock frequency. + * n: bus clock/(2^(n+1)) */ +#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */ #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ (1 << 9) | (1 << 8)) /* resp busy timeout */ @@ -185,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base) /* Set block size in MMCIF hardware */ sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); - /* Enable the clock, set it to Bus clock/256 (about 325Khz). - * It is unclear where 0x70000 comes from or if it is even needed. - * It is there for byte-compatibility with code that is known to - * work. - */ + /* Enable the clock, set it to Bus clock/256 (about 325Khz). */ sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, - CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | - SCCSTO_29 | 0x70000); + CLK_ENABLE | CLKDIV_256 | SRSPTO_256 | + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); /* CMD0 */ sh_mmcif_boot_cmd(base, 0x00000040, 0); @@ -216,8 +215,12 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base, { unsigned long tmp; + return; + /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */ - sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff); + sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, + CLK_ENABLE | CLKDIV_4 | SRSPTO_256 | + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); /* CMD9 - Get CSD */ sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);