From patchwork Tue Feb 15 09:35:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arindam Nath X-Patchwork-Id: 558381 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p1F9bBK5026706 for ; Tue, 15 Feb 2011 09:37:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754454Ab1BOJhK (ORCPT ); Tue, 15 Feb 2011 04:37:10 -0500 Received: from mail-iy0-f174.google.com ([209.85.210.174]:52231 "EHLO mail-iy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753787Ab1BOJhJ (ORCPT ); Tue, 15 Feb 2011 04:37:09 -0500 Received: by iyj8 with SMTP id 8so5729998iyj.19 for ; Tue, 15 Feb 2011 01:37:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=32TH7xRQ0ZPRGOLMtFKSezoUugi53NcISLXjifVIW0I=; b=DzCxkwfmGYZWn0U6bK5Wlzdx7d1tN45qHv+NXH31kE+L6Hr1OOw1Z5Ro7v05uezSZH 06CaivavExOV5BByo9Cpc7qA81cVDESVO0bavOsnTHDCZ22cB3etxYd9pK8MjXsAdZZk qfOUAiae4obqEerJLa0NkjIaImoKHHgzCvGa8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=NSwYLONHKSCpK2tauGZHeaR6+ihZLdDn4jqRo9MpE+HUThRptrSg3fmzZCZxkMRwxA u670SEPK/sdpOPy9roezo0mBUkB0YRXTnmcxp7GBubHKXKxtb2crCX+Fx3ukhJSrktaG wgFmnNc8VwDnKKgl10Mnt16S+BzszLY2SHdMw= Received: by 10.42.164.73 with SMTP id f9mr6227779icy.156.1297762629180; Tue, 15 Feb 2011 01:37:09 -0800 (PST) Received: from localhost ([122.167.0.108]) by mx.google.com with ESMTPS id ey6sm3057990icb.17.2011.02.15.01.37.03 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 15 Feb 2011 01:37:08 -0800 (PST) From: Arindam Nath To: cjb@laptop.org Cc: linux-mmc@vger.kernel.org, henry.su@amd.com, aaron.lu@amd.com, anath.amd@gmail.com, Arindam Nath Subject: [PATCH 05/12] mmc: sdhci: reset sdclk before setting high speed enable Date: Tue, 15 Feb 2011 15:05:03 +0530 Message-Id: <1297762510-2696-6-git-send-email-arindam.nath@amd.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297762510-2696-1-git-send-email-arindam.nath@amd.com> References: <1297762510-2696-1-git-send-email-arindam.nath@amd.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 15 Feb 2011 09:37:11 +0000 (UTC) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index b768839..5db0109 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1280,13 +1280,12 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) else ctrl &= ~SDHCI_CTRL_HISPD; - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); - if (host->version >= SDHCI_SPEC_300) { u16 ctrl_2; ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * We only need to set Driver Strength if the * preset value enable is not set. @@ -1297,8 +1296,28 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } else { + /* + * According to SDHC Spec v3.00, if the Preset Value + * Enable in the Host Control 2 register is set, we + * need to reset SD Clock Enable before changing High + * Speed Enable to avoid generating clock gliches. + */ + u16 clk; + + /* Reset SD Clock Enable */ + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); + + /* Re-enable SD Clock */ + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); } - } + } else + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * Some (ENE) controllers go apeshit on some ios operation,