From patchwork Sat Feb 26 12:40:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 592411 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p1QCWSSp031673 for ; Sat, 26 Feb 2011 12:32:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752152Ab1BZMc1 (ORCPT ); Sat, 26 Feb 2011 07:32:27 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:55907 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752117Ab1BZMc0 (ORCPT ); Sat, 26 Feb 2011 07:32:26 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p1QCWIRS025056 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 26 Feb 2011 06:32:20 -0600 Received: from ucmsshproxy.india.ext.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with SMTP id p1QCWCvi022088; Sat, 26 Feb 2011 18:02:13 +0530 (IST) Received: from localhost (unknown [10.24.244.160]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id 6014F158002; Sat, 26 Feb 2011 18:02:12 +0530 (IST) From: Kishore Kadiyala To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: tony@atomide.com, cjb@laptop.org, madhu.cr@ti.com, khilman@deeprootsystems.com, paul@pwsan.com, b-cousson@ti.com, Kishore Kadiyala Subject: [RESEND v5 PATCH 2/8] OMAP2430: hwmod data: Add HSMMC Date: Sat, 26 Feb 2011 18:10:03 +0530 Message-Id: <1298724004-26018-1-git-send-email-kishore.kadiyala@ti.com> X-Mailer: git-send-email 1.7.1 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sat, 26 Feb 2011 12:32:34 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index de0015d..cba1800 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -54,6 +54,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod; static struct omap_hwmod omap2430_mcspi1_hwmod; static struct omap_hwmod omap2430_mcspi2_hwmod; static struct omap_hwmod omap2430_mcspi3_hwmod; +static struct omap_hwmod omap2430_mmc1_hwmod; +static struct omap_hwmod omap2430_mmc2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -250,6 +252,42 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { &omap2430_l4_core__usbhsotg, }; +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c1ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b41ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc2_hwmod, + .addr = omap2430_mmc2_addr_space, + .clk = "mmchs2_ick", + .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { &omap2430_l3_main__l4_core, @@ -258,6 +296,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { &omap2430_l4_core__l4_wkup, + &omap2430_l4_core__mmc1, + &omap2430_l4_core__mmc2, }; /* L4 CORE */ @@ -1508,6 +1548,112 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { +/* MMC/SD/SDIO common */ + +static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mmc_class = { + .name = "mmc", + .sysc = &omap2430_mmc_sysc, +}; + +/* MMC/SD/SDIO1 */ + +static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { + { .irq = 83 }, +}; + +static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { + { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ + { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ +}; + +static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb1_fck" }, +}; + +static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { + &omap2430_l4_core__mmc1, +}; + +static struct omap_hwmod omap2430_mmc1_hwmod = { + .name = "mmc1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2430_mmc1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs), + .sdma_reqs = omap2430_mmc1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs), + .opt_clks = omap2430_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS1_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, + }, + }, + .slaves = omap2430_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), + .class = &omap2430_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* MMC/SD/SDIO2 */ + +static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { + { .irq = 86 }, +}; + +static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { + { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ + { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ +}; + +static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb2_fck" }, +}; + +static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { + &omap2430_l4_core__mmc2, +}; + +static struct omap_hwmod omap2430_mmc2_hwmod = { + .name = "mmc2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2430_mmc2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs), + .sdma_reqs = omap2430_mmc2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs), + .opt_clks = omap2430_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS2_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, + }, + }, + .slaves = omap2430_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), + .class = &omap2430_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, @@ -1526,6 +1672,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { /* i2c class */ &omap2430_i2c1_hwmod, &omap2430_i2c2_hwmod, + &omap2430_mmc1_hwmod, + &omap2430_mmc2_hwmod, /* gpio class */ &omap2430_gpio1_hwmod,