From patchwork Thu May 5 06:49:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arindam Nath X-Patchwork-Id: 755982 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p456orZc020427 for ; Thu, 5 May 2011 06:50:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751384Ab1EEGu4 (ORCPT ); Thu, 5 May 2011 02:50:56 -0400 Received: from mail-pv0-f174.google.com ([74.125.83.174]:54796 "EHLO mail-pv0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751025Ab1EEGuz (ORCPT ); Thu, 5 May 2011 02:50:55 -0400 Received: by pvg12 with SMTP id 12so837031pvg.19 for ; Wed, 04 May 2011 23:50:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=1wHn+010vZc6JIAmyVyCxA01seVs1sT7lutEWE/bw7Q=; b=HBVrkUBe+f+nOuLakfrdM+z2JwTlaR9mt+oNceIrWh1hrL9Ujy8f5vLQbqHSqRX/F1 ojj5+hvXNVGcGitIgUI9DwYNwz91EdKgvM/fk+Ms6M4n3v+Julhr2TtcpQqYj9x2LIn6 kgWJRIl04Rrk77OfE14tUCL2sQiWOr35R4EHQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=j7x6gWhypAcJsMUjdaTEu6iDeaCxLy88FSi5YzEUp8WePUh2+CIgup5eGjzpJ0RF4c S9WFhBWoI/5Cu+cSanHBj0kzy0lK+N88ieFbVaZ6jm66iOOEuq8o+kQdtxSs5ioOUjxf mbsycuYQ4J2RpyTVIlW4NMSrzAQozXf/N61/U= Received: by 10.68.20.163 with SMTP id o3mr2287030pbe.366.1304578255167; Wed, 04 May 2011 23:50:55 -0700 (PDT) Received: from localhost ([122.166.82.113]) by mx.google.com with ESMTPS id 8sm1241845pbw.23.2011.05.04.23.50.47 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 May 2011 23:50:54 -0700 (PDT) From: Arindam Nath To: cjb@laptop.org Cc: prakity@marvell.com, zhangfei.gao@gmail.com, subhashj@codeaurora.org, linux-mmc@vger.kernel.org, henry.su@amd.com, aaron.lu@amd.com, anath.amd@gmail.com, Arindam Nath Subject: [PATCH v4 04/15] mmc: sdhci: reset sdclk before setting high speed enable Date: Thu, 5 May 2011 12:19:00 +0530 Message-Id: <1304578151-1775-5-git-send-email-arindam.nath@amd.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1304578151-1775-1-git-send-email-arindam.nath@amd.com> References: <1304578151-1775-1-git-send-email-arindam.nath@amd.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 05 May 2011 06:50:56 +0000 (UTC) As per Host Controller spec v3.00, we reset SDCLK before setting High Speed Enable, and then set it back to avoid generating clock gliches. Before enabling SDCLK again, we make sure the clock is stable, so we use sdhci_set_clock(). Signed-off-by: Arindam Nath Reviewed-by: Philip Rakity Tested-by: Philip Rakity --- drivers/mmc/host/sdhci.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9f38317..309240c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1243,13 +1243,12 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) else ctrl &= ~SDHCI_CTRL_HISPD; - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); - if (host->version >= SDHCI_SPEC_300) { u16 ctrl_2; ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * We only need to set Driver Strength if the * preset value enable is not set. @@ -1261,8 +1260,30 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } else { + /* + * According to SDHC Spec v3.00, if the Preset Value + * Enable in the Host Control 2 register is set, we + * need to reset SD Clock Enable before changing High + * Speed Enable to avoid generating clock gliches. + */ + u16 clk; + unsigned int clock; + + /* Reset SD Clock Enable */ + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); + + /* Re-enable SD Clock */ + clock = host->clock; + host->clock = 0; + sdhci_set_clock(host, clock); } - } + } else + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * Some (ENE) controllers go apeshit on some ios operation,