From patchwork Thu Jun 2 09:12:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 842992 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p529CO8U030438 for ; Thu, 2 Jun 2011 09:12:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932491Ab1FBJMY (ORCPT ); Thu, 2 Jun 2011 05:12:24 -0400 Received: from ch1ehsobe001.messaging.microsoft.com ([216.32.181.181]:41989 "EHLO CH1EHSOBE006.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932164Ab1FBJMW (ORCPT ); Thu, 2 Jun 2011 05:12:22 -0400 Received: from mail196-ch1-R.bigfish.com (216.32.181.174) by CH1EHSOBE006.bigfish.com (10.43.70.56) with Microsoft SMTP Server id 14.1.225.22; Thu, 2 Jun 2011 09:12:21 +0000 Received: from mail196-ch1 (localhost.localdomain [127.0.0.1]) by mail196-ch1-R.bigfish.com (Postfix) with ESMTP id 4EFBA1C8818A; Thu, 2 Jun 2011 09:12:21 +0000 (UTC) X-SpamScore: 4 X-BigFish: VS4(zzb922lzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail196-ch1 (localhost.localdomain [127.0.0.1]) by mail196-ch1 (MessageSwitch) id 1307005941116977_20800; Thu, 2 Jun 2011 09:12:21 +0000 (UTC) Received: from CH1EHSMHS022.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.247]) by mail196-ch1.bigfish.com (Postfix) with ESMTP id 0DB3B1B2804B; Thu, 2 Jun 2011 09:12:21 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS022.bigfish.com (10.43.70.22) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 2 Jun 2011 09:12:20 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.289.8; Thu, 2 Jun 2011 04:12:19 -0500 Received: from x-VirtualBox.ap.freescale.net ([10.192.242.64]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p529CE90024149; Thu, 2 Jun 2011 04:12:15 -0500 (CDT) From: Richard Zhu To: CC: , , , , , , Richard Zhu Subject: [RFC] mmc: Enable the ADMA on esdhc imx driver Date: Thu, 2 Jun 2011 17:12:10 +0800 Message-ID: <1307005930-10935-1-git-send-email-richard.zhu@linaro.org> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 02 Jun 2011 09:12:25 +0000 (UTC) Eanble the ADMA mode on freescale esdhc imx driver, tested on MX51 and MX53. Signed-off-by: Richard Zhu --- drivers/mmc/host/sdhci-esdhc-imx.c | 40 ++++++++++++++++++++++++++++++----- 1 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index a19967d..64f33cb 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -31,6 +31,8 @@ #define SDHCI_VENDOR_SPEC 0xC0 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 +#define SDHCI_VENDOR_SPEC_INT_ADMA_ERR 0x10000000 + #define ESDHC_FLAG_GPIO_FOR_CD_WP (1 << 0) /* * The CMDTYPE of the CMD register (offset 0xE) should be set to @@ -80,6 +82,20 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val |= SDHCI_CARD_PRESENT; } + if (unlikely(reg == SDHCI_CAPABILITIES)) { + if (val & SDHCI_CAN_DO_ADMA1) { + val &= ~SDHCI_CAN_DO_ADMA1; + val |= SDHCI_CAN_DO_ADMA2; + } + } + + if (unlikely(reg == SDHCI_INT_STATUS)) { + if (val & SDHCI_VENDOR_SPEC_INT_ADMA_ERR) { + val &= ~SDHCI_VENDOR_SPEC_INT_ADMA_ERR; + val |= SDHCI_INT_ADMA_ERROR; + } + } + return val; } @@ -105,6 +121,13 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); } + if (unlikely((reg == SDHCI_INT_ENABLE) + || (reg == SDHCI_SIGNAL_ENABLE))) { + if (val & SDHCI_INT_ADMA_ERROR) { + val &= ~SDHCI_INT_ADMA_ERROR; + val |= SDHCI_VENDOR_SPEC_INT_ADMA_ERR; + } + } writel(val, host->ioaddr + reg); } @@ -166,12 +189,16 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) case SDHCI_HOST_CONTROL: /* FSL messed up here, so we can just keep those two */ new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS); - /* ensure the endianess */ + /* ensure the endi1ness */ new_val |= ESDHC_HOST_CONTROL_LE; - /* DMA mode bits are shifted */ - new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; + if (val & SDHCI_CTRL_DMA_MASK) { + /* DMA mode bits are shifted */ + new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; + + esdhc_clrset_le(host, 0xffff, new_val, reg); + } else + esdhc_clrset_le(host, 0xff, val, reg); - esdhc_clrset_le(host, 0xffff, new_val, reg); return; } esdhc_clrset_le(host, 0xff, val, reg); @@ -322,9 +349,10 @@ static void esdhc_pltfm_exit(struct sdhci_host *host) } struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { - .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA + .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT + | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC + | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_BROKEN_CARD_DETECTION, - /* ADMA has issues. Might be fixable */ .ops = &sdhci_esdhc_ops, .init = esdhc_pltfm_init, .exit = esdhc_pltfm_exit,