From patchwork Tue Jul 5 04:19:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zang Roy-R61911 X-Patchwork-Id: 943322 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p653qKjc001024 for ; Tue, 5 Jul 2011 03:52:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752841Ab1GEDkx (ORCPT ); Mon, 4 Jul 2011 23:40:53 -0400 Received: from db3ehsobe004.messaging.microsoft.com ([213.199.154.142]:54954 "EHLO DB3EHSOBE004.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752674Ab1GEDkx (ORCPT ); Mon, 4 Jul 2011 23:40:53 -0400 Received: from mail107-db3-R.bigfish.com (10.3.81.246) by DB3EHSOBE004.bigfish.com (10.3.84.24) with Microsoft SMTP Server id 14.1.225.22; Tue, 5 Jul 2011 03:40:52 +0000 Received: from mail107-db3 (localhost.localdomain [127.0.0.1]) by mail107-db3-R.bigfish.com (Postfix) with ESMTP id EDF3E10024B; Tue, 5 Jul 2011 03:40:51 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail107-db3 (localhost.localdomain [127.0.0.1]) by mail107-db3 (MessageSwitch) id 1309837251626561_11183; Tue, 5 Jul 2011 03:40:51 +0000 (UTC) Received: from DB3EHSMHS002.bigfish.com (unknown [10.3.81.247]) by mail107-db3.bigfish.com (Postfix) with ESMTP id 89EA410C804F; Tue, 5 Jul 2011 03:40:51 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS002.bigfish.com (10.3.87.102) with Microsoft SMTP Server (TLS) id 14.1.225.22; Tue, 5 Jul 2011 03:40:49 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.289.8; Mon, 4 Jul 2011 22:40:47 -0500 Received: from localhost.localdomain (udp144289uds.ap.freescale.net [10.193.20.43]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p653edAk029881; Mon, 4 Jul 2011 22:40:45 -0500 (CDT) From: Roy Zang To: CC: , , , Roy Zang Subject: [PATCH 3/3] eSDHC: fix incorrect default value of the capabilities register on P4080 Date: Tue, 5 Jul 2011 12:19:03 +0800 Message-ID: <1309839543-6031-3-git-send-email-tie-fei.zang@freescale.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <1309839543-6031-2-git-send-email-tie-fei.zang@freescale.com> References: <1309839543-6031-1-git-send-email-tie-fei.zang@freescale.com> <1309839543-6031-2-git-send-email-tie-fei.zang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 05 Jul 2011 03:52:21 +0000 (UTC) P4080 eSDHC errata 12 describes incorrect default value of the the host controller capabilities register. The default value of the VS18 and VS30 fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one in the eSDHC logic. This patch adds the workaround for these errata. Signed-off-by: Roy Zang --- drivers/mmc/host/sdhci-of-core.c | 3 +++ drivers/mmc/host/sdhci.c | 6 ++++++ include/linux/mmc/sdhci.h | 4 ++++ 3 files changed, 13 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c index fede43d..9bdd30d 100644 --- a/drivers/mmc/host/sdhci-of-core.c +++ b/drivers/mmc/host/sdhci-of-core.c @@ -182,6 +182,9 @@ static int __devinit sdhci_of_probe(struct platform_device *ofdev) if (of_device_is_compatible(np, "fsl,esdhc")) host->quirks |= SDHCI_QUIRK_QORIQ_PROCTL_WEIRD; + if (of_device_is_compatible(np, "fsl,p4080-esdhc")) + host->quirks |= SDHCI_QUIRK_QORIQ_HOSTCAPBLT_ONLY_VS33; + clk = of_get_property(np, "clock-frequency", &size); if (clk && size == sizeof(*clk) && *clk) of_host->clock = be32_to_cpup(clk); diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 77174e5..7e0b4cd 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2396,6 +2396,12 @@ int sdhci_add_host(struct sdhci_host *host) caps[1] = (host->version >= SDHCI_SPEC_300) ? sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0; + /* Make sure clean the VS18 and VS30 bit. P4080 incorrectly + * set the voltage capability bits + */ + if (host->quirks & SDHCI_QUIRK_QORIQ_HOSTCAPBLT_ONLY_VS33) + caps[0] &= ~(SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300); + if (host->quirks & SDHCI_QUIRK_FORCE_DMA) host->flags |= SDHCI_USE_SDMA; else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index d87abc7..7ffd458 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -89,6 +89,10 @@ struct sdhci_host { #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1U<<31) /* Controller has weird bit setting for Protocol Control Register */ #define SDHCI_QUIRK_QORIQ_PROCTL_WEIRD (0x100000000U) +/* Controller can only supports 3.3V, but the capabilities register + * has incorrect set 1.8V and 3.0V + */ +#define SDHCI_QUIRK_QORIQ_HOSTCAPBLT_ONLY_VS33 (0x200000000U) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */