From patchwork Thu Jul 7 21:33:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Yariv X-Patchwork-Id: 954322 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p67LXOCc006216 for ; Thu, 7 Jul 2011 21:33:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751700Ab1GGVd2 (ORCPT ); Thu, 7 Jul 2011 17:33:28 -0400 Received: from mail-ww0-f44.google.com ([74.125.82.44]:41458 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751615Ab1GGVd1 (ORCPT ); Thu, 7 Jul 2011 17:33:27 -0400 Received: by mail-ww0-f44.google.com with SMTP id 5so1362105wwe.1 for ; Thu, 07 Jul 2011 14:33:26 -0700 (PDT) Received: by 10.216.68.2 with SMTP id k2mr57007wed.0.1310074406871; Thu, 07 Jul 2011 14:33:26 -0700 (PDT) Received: from localhost.localdomain (46-116-74-128.bb.netvision.net.il [46.116.74.128]) by mx.google.com with ESMTPS id k57sm134149wed.34.2011.07.07.14.33.24 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jul 2011 14:33:26 -0700 (PDT) From: Ido Yariv To: davinci-linux-open-source@linux.davincidsp.com, linux-arm-kernel@lists.arm.linux.org.uk, linux-mmc@vger.kernel.org Cc: Ido Yariv Subject: [PATCH 2/5] arm: davinci: Allow EVENTQ_0 as a default queue Date: Fri, 8 Jul 2011 00:33:07 +0300 Message-Id: <1310074390-4277-3-git-send-email-ido@wizery.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1310074390-4277-1-git-send-email-ido@wizery.com> References: <1310074390-4277-1-git-send-email-ido@wizery.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 07 Jul 2011 21:33:28 +0000 (UTC) Davinci platforms may define a default queue for each channel controller. If one is not defined, the default queue is set to EVENTQ_1. However, there's no way to distinguish between an unset default queue to one that is set to EVENTQ_0, as EVENTQ_0 = 0. In order to keep existing behaviour on platforms which don't specify a default_queue member, the default_queue member was modified to be a pointer to enum dma_event_q. A NULL value means that this member was not specified. Signed-off-by: Ido Yariv --- arch/arm/mach-davinci/dm365.c | 4 +++- arch/arm/mach-davinci/dma.c | 5 +++-- arch/arm/mach-davinci/include/mach/edma.h | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 4604e72..b1cf08e 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -827,6 +827,8 @@ dm365_queue_priority_mapping[][2] = { {-1, -1}, }; +static enum dma_event_q dm365_edma_cc0_default_queue = EVENTQ_3; + static struct edma_soc_info edma_cc0_info = { .n_channel = 64, .n_region = 4, @@ -835,7 +837,7 @@ static struct edma_soc_info edma_cc0_info = { .n_cc = 1, .queue_tc_mapping = dm365_queue_tc_mapping, .queue_priority_mapping = dm365_queue_priority_mapping, - .default_queue = EVENTQ_3, + .default_queue_ptr = &dm365_edma_cc0_default_queue, }; static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = { diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 6b96698..11c71e7 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -1449,8 +1449,9 @@ static int __init edma_probe(struct platform_device *pdev) edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc, EDMA_MAX_CC); - edma_cc[j]->default_queue = info[j]->default_queue; - if (!edma_cc[j]->default_queue) + if (info[j]->default_queue_ptr) + edma_cc[j]->default_queue = *info[j]->default_queue_ptr; + else edma_cc[j]->default_queue = EVENTQ_1; dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 20c77f2..7f81812 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -250,7 +250,7 @@ struct edma_soc_info { unsigned n_slot; unsigned n_tc; unsigned n_cc; - enum dma_event_q default_queue; + enum dma_event_q *default_queue_ptr; /* Resource reservation for other cores */ struct edma_rsv_info *rsv;