From patchwork Thu Jul 7 21:33:08 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Yariv X-Patchwork-Id: 954342 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p67LXOCd006216 for ; Thu, 7 Jul 2011 21:33:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751829Ab1GGVda (ORCPT ); Thu, 7 Jul 2011 17:33:30 -0400 Received: from mail-ww0-f44.google.com ([74.125.82.44]:41458 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751651Ab1GGVd3 (ORCPT ); Thu, 7 Jul 2011 17:33:29 -0400 Received: by mail-ww0-f44.google.com with SMTP id 5so1362105wwe.1 for ; Thu, 07 Jul 2011 14:33:29 -0700 (PDT) Received: by 10.216.187.65 with SMTP id x43mr1109466wem.62.1310074408993; Thu, 07 Jul 2011 14:33:28 -0700 (PDT) Received: from localhost.localdomain (46-116-74-128.bb.netvision.net.il [46.116.74.128]) by mx.google.com with ESMTPS id k57sm134149wed.34.2011.07.07.14.33.27 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jul 2011 14:33:28 -0700 (PDT) From: Ido Yariv To: davinci-linux-open-source@linux.davincidsp.com, linux-arm-kernel@lists.arm.linux.org.uk, linux-mmc@vger.kernel.org Cc: Ido Yariv Subject: [PATCH 3/5] arm: davinci: DA850: Set a default queue for CC1 Date: Fri, 8 Jul 2011 00:33:08 +0300 Message-Id: <1310074390-4277-4-git-send-email-ido@wizery.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1310074390-4277-1-git-send-email-ido@wizery.com> References: <1310074390-4277-1-git-send-email-ido@wizery.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 07 Jul 2011 21:33:30 +0000 (UTC) If a default queue is not set for a channel controller, EVENTQ_1 is used. The second channel controller has only one event queue, and so, EVENTQ_1 is an invalid option. Fix this by explicitly setting the default queue for CC1 to be EVENTQ_0. Signed-off-by: Ido Yariv --- arch/arm/mach-davinci/devices-da8xx.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index fc4e98e..74114c0 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -139,6 +139,8 @@ static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { &da830_edma_cc0_info, }; +static enum dma_event_q da850_edma_cc1_default_queue = EVENTQ_0; + static struct edma_soc_info da850_edma_cc_info[] = { { .n_channel = 32, @@ -157,6 +159,7 @@ static struct edma_soc_info da850_edma_cc_info[] = { .n_cc = 1, .queue_tc_mapping = da850_queue_tc_mapping, .queue_priority_mapping = da850_queue_priority_mapping, + .default_queue_ptr = &da850_edma_cc1_default_queue, }, };