From patchwork Tue Sep 11 11:58:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 1437381 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 91AC73FC33 for ; Tue, 11 Sep 2012 12:02:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932146Ab2IKMC1 (ORCPT ); Tue, 11 Sep 2012 08:02:27 -0400 Received: from na3sys009aog107.obsmtp.com ([74.125.149.197]:37062 "EHLO na3sys009aog107.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932143Ab2IKMC1 (ORCPT ); Tue, 11 Sep 2012 08:02:27 -0400 Received: from MSI-MTA.marvell.com ([65.219.4.132]) (using TLSv1) by na3sys009aob107.postini.com ([74.125.148.12]) with SMTP ID DSNKUE8oS+l9iYwO7J4/30xY9S28Tw6Rb7HB@postini.com; Tue, 11 Sep 2012 05:02:26 PDT Received: from maili.marvell.com ([10.68.76.210]) by MSI-MTA.marvell.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 11 Sep 2012 05:02:10 -0700 Received: from localhost.localdomain (unknown [10.38.36.240]) by maili.marvell.com (Postfix) with ESMTP id C31224E510; Tue, 11 Sep 2012 05:02:09 -0700 (PDT) From: Kevin Liu To: linux-mmc@vger.kernel.org, cjb@laptop.org, pierre@ossman.eu Cc: cxie4@marvell.com, hzhuang1@marvell.com, prakity@marvell.com, kliu5@marvell.com Subject: [PATCH] mmc: sdhci: refine code for sd clock disable/enable in set ios Date: Tue, 11 Sep 2012 19:58:46 +0800 Message-Id: <1347364726-21492-1-git-send-email-keyuan.liu@gmail.com> X-Mailer: git-send-email 1.7.0.4 X-OriginalArrivalTime: 11 Sep 2012 12:02:10.0905 (UTC) FILETIME=[46236490:01CD9015] Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Kevin Liu With preset value enabled, there are two continuous times of sd clock disable/enable. They can be combined into one to save time and make code cleaner. Signed-off-by: Kevin Liu --- drivers/mmc/host/sdhci.c | 29 +++++++++-------------------- 1 files changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 8c56435..9b619e9 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1441,33 +1441,22 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); - } else { - /* - * According to SDHC Spec v3.00, if the Preset Value - * Enable in the Host Control 2 register is set, we - * need to reset SD Clock Enable before changing High - * Speed Enable to avoid generating clock gliches. - */ - - /* Reset SD Clock Enable */ - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - clk &= ~SDHCI_CLOCK_CARD_EN; - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - - /* Re-enable SD Clock */ - clock = host->clock; - host->clock = 0; - sdhci_set_clock(host, clock); } - /* Reset SD Clock Enable */ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); clk &= ~SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + /* + * According to SDHC Spec v3.00, if the Preset Value + * Enable in the Host Control 2 register is set, we + * need to reset SD Clock Enable before changing High + * Speed Enable to avoid generating clock gliches. + */ + if (ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE) + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + if (host->ops->set_uhs_signaling) host->ops->set_uhs_signaling(host, ios->timing); else {