From patchwork Thu Nov 15 18:25:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Cooper X-Patchwork-Id: 1751391 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 657493FCA5 for ; Thu, 15 Nov 2012 18:58:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1768684Ab2KOS6b (ORCPT ); Thu, 15 Nov 2012 13:58:31 -0500 Received: from mms2.broadcom.com ([216.31.210.18]:3749 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1768697Ab2KOS6b (ORCPT ); Thu, 15 Nov 2012 13:58:31 -0500 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Thu, 15 Nov 2012 10:55:46 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Thu, 15 Nov 2012 10:57:03 -0800 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 99FC540FE4; Thu, 15 Nov 2012 10:57:29 -0800 (PST) From: "Al Cooper" To: cjb@laptop.org, linux-mmc@vger.kernel.org cc: "Al Cooper" Subject: [PATCH] mmc: Limit MMC speed to 52MHz if not HS200 Date: Thu, 15 Nov 2012 13:25:22 -0500 Message-ID: <1353003922-1631-1-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: References: MIME-Version: 1.0 X-WSS-ID: 7CBBE5383R02988574-07-01 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org If "caps2" host capabilities does not indicate support for MMC HS200, don't allow clock speeds >52MHz. Currently, for MMC, the clock speed is set to the lesser of the max speed the eMMC module supports (card->ext_csd.hs_max_dtr) or the max base clock of the host controller (host->f_max based on BASE_CLK_FREQ in the host CAPS register). This means that a host controller that doesn't support HS200 mode but has a base clock of 100MHz and an eMMC module that supports HS200 speeds will end up using a 100MHz clock. Signed-off-by: Al Cooper --- drivers/mmc/core/mmc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 7cc4638..6d669c3 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1051,6 +1051,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, if (mmc_card_highspeed(card) || mmc_card_hs200(card)) { if (max_dtr > card->ext_csd.hs_max_dtr) max_dtr = card->ext_csd.hs_max_dtr; + if (mmc_card_highspeed(card) && (max_dtr > 52000000)) + max_dtr = 52000000; } else if (max_dtr > card->csd.max_dtr) { max_dtr = card->csd.max_dtr; }