From patchwork Wed Dec 12 14:38:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 1867311 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id BCD8ADF215 for ; Wed, 12 Dec 2012 14:38:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754599Ab2LLOig (ORCPT ); Wed, 12 Dec 2012 09:38:36 -0500 Received: from moutng.kundenserver.de ([212.227.126.171]:52177 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754586Ab2LLOia (ORCPT ); Wed, 12 Dec 2012 09:38:30 -0500 Received: from axis700.grange (dslb-146-060-250-080.pools.arcor-ip.net [146.60.250.80]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0M1uF5-1SqYy54BJb-00u2oP; Wed, 12 Dec 2012 15:38:23 +0100 Received: from 6a.grange (6a.grange [192.168.1.11]) by axis700.grange (Postfix) with ESMTPS id 895AD105E9; Wed, 12 Dec 2012 15:38:21 +0100 (CET) Received: from lyakh by 6a.grange with local (Exim 4.72) (envelope-from ) id 1TinRy-0004iA-Ob; Wed, 12 Dec 2012 15:38:18 +0100 From: Guennadi Liakhovetski To: linux-mmc@vger.kernel.org Cc: linux-sh@vger.kernel.org, Magnus Damm , Chris Ball , Teppei Kamijou , Shinya Kuribayashi Subject: [PATCH 04/14] mmc: sh_mmcif: Add support for eMMC Dual Data Rate Date: Wed, 12 Dec 2012 15:38:08 +0100 Message-Id: <1355323098-18061-5-git-send-email-g.liakhovetski@gmx.de> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1355323098-18061-1-git-send-email-g.liakhovetski@gmx.de> References: <1355323098-18061-1-git-send-email-g.liakhovetski@gmx.de> X-Provags-ID: V02:K0:xL8tlz2kNsb5b4D0UbnB/GldGu4LX/fb+ImggJcRJsG 39SPa2m4tIpDbH21wcVEKrj9dxVuP+W3Pf8LJwpnCfGGrS6rCK 1DmS1GPmHV2eHO2YIBQUgqTOHvvMY4dGhROrwrbUL4O7DLnMUC C/ss5AJ4lCokjiy0jq37y3Zb7kejav4wOtce17Iuv0gWYrbLjH 8eOQOV/RLOIPdc1mkDdtY934qCM3kJR4k9M7yFfTjKxlkbaCmN na3PML6Iac/RzcFLdGqA4qEwT1cnFhx0okt/h75Bx/EGJMym+P VFYDgkOTYy756AOnIaED/rMG9g3N5GVELE/DjJGapj8+va5KqC JYLyY/DGnSX7GFQnnVqb8T1wf4+cLoEDNG5lmirY9sCY2PB2ik cPN6ThUG9O5aQ== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Teppei Kamijou Some MMCIF implementations support the Dual Data Rate. With this patch, platforms can set the MMC_CAP_UHS_DDR50 capability flag in MMCIF platform data. This will let the MMC core to actually use the DDR mode. Signed-off-by: Teppei Kamijou Signed-off-by: Shinya Kuribayashi Signed-off-by: Guennadi Liakhovetski --- drivers/mmc/host/sh_mmcif.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index d80c294..1ec3339 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -88,6 +88,7 @@ #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ #define CMD_SET_CCSH (1 << 5) +#define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ @@ -216,6 +217,7 @@ struct sh_mmcif_host { struct clk *hclk; unsigned int clk; int bus_width; + unsigned char timing; bool sd_error; bool dying; long timeout; @@ -781,6 +783,17 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, dev_err(&host->pd->dev, "Unsupported bus width.\n"); break; } + switch (host->timing) { + case MMC_TIMING_UHS_DDR50: + /* + * MMC core will only set this timing, if the host + * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF + * implementations with this capability, e.g. sh73a0, + * will have to set it in their platform data. + */ + tmp |= CMD_SET_DARS; + break; + } } /* DWEN */ if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) @@ -1002,6 +1015,7 @@ static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) sh_mmcif_clock_control(host, ios->clock); } + host->timing = ios->timing; host->bus_width = ios->bus_width; host->state = STATE_IDLE; }