From patchwork Wed Dec 12 15:50:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 1867771 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id DF5B0DF266 for ; Wed, 12 Dec 2012 15:50:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754314Ab2LLPuk (ORCPT ); Wed, 12 Dec 2012 10:50:40 -0500 Received: from eu1sys200aog115.obsmtp.com ([207.126.144.139]:44265 "EHLO eu1sys200aog115.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754361Ab2LLPuj (ORCPT ); Wed, 12 Dec 2012 10:50:39 -0500 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKUMinxvcatukGVo3NUvrni5OC79ep68H7@postini.com; Wed, 12 Dec 2012 15:50:38 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9FD0868; Wed, 12 Dec 2012 15:50:24 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1BF454DE7; Wed, 12 Dec 2012 15:50:24 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id A3EBAA8065; Wed, 12 Dec 2012 16:50:17 +0100 (CET) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 12 Dec 2012 16:50:23 +0100 From: Ulf Hansson To: , Chris Ball Cc: , Russell King , Linus Walleij , Johan Rudholm , Ulf Hansson Subject: [PATCH] mmc: mmci: Gate the clock when freq is 0 Date: Wed, 12 Dec 2012 16:50:21 +0100 Message-ID: <1355327421-20187-1-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Johan Rudholm In the ST Micro variant, the MMCI_CLOCK register should not be used to gate the clock. Use MMCI_POWER to do this. Signed-off-by: Johan Rudholm Signed-off-by: Ulf Hansson Acked-by: Linus Walleij --- drivers/mmc/host/mmci.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index edc3e9b..bf07823 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -1147,6 +1147,15 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) } } + /* + * If clock = 0 and the block needs a certain value in the clreg + * to function, we need to gate the clock by removing MCI_PWR_ON. + * This is a special case for ST Micro variants, since the power + * register in the ARM legacy case is used for powering the cards. + */ + if (!ios->clock && variant->clkreg) + pwr &= ~MCI_PWR_ON; + spin_lock_irqsave(&host->lock, flags); mmci_set_clkreg(host, ios->clock);