From patchwork Tue May 14 22:52:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2569001 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 46BE0DF24C for ; Tue, 14 May 2013 23:06:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758565Ab3ENXGD (ORCPT ); Tue, 14 May 2013 19:06:03 -0400 Received: from mail-db9lp0253.outbound.messaging.microsoft.com ([213.199.154.253]:45875 "EHLO db9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758431Ab3ENXGB (ORCPT ); Tue, 14 May 2013 19:06:01 -0400 X-Greylist: delayed 903 seconds by postgrey-1.27 at vger.kernel.org; Tue, 14 May 2013 19:06:01 EDT Received: from mail92-db9-R.bigfish.com (10.174.16.237) by DB9EHSOBE017.bigfish.com (10.174.14.80) with Microsoft SMTP Server id 14.1.225.23; Tue, 14 May 2013 22:50:56 +0000 Received: from mail92-db9 (localhost [127.0.0.1]) by mail92-db9-R.bigfish.com (Postfix) with ESMTP id 7650B420AB9; Tue, 14 May 2013 22:50:56 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6hzz8275bh8275dh8275chz2fh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1155h) Received-SPF: pass (mail92-db9: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail92-db9 (localhost.localdomain [127.0.0.1]) by mail92-db9 (MessageSwitch) id 1368571854729459_14973; Tue, 14 May 2013 22:50:54 +0000 (UTC) Received: from DB9EHSMHS018.bigfish.com (unknown [10.174.16.241]) by mail92-db9.bigfish.com (Postfix) with ESMTP id A4B6514009F; Tue, 14 May 2013 22:50:54 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by DB9EHSMHS018.bigfish.com (10.174.14.28) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 14 May 2013 22:50:52 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.298.1; Tue, 14 May 2013 15:41:02 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r4EMojmC001192; Tue, 14 May 2013 15:50:50 -0700 (PDT) From: To: CC: , Dinh Nguyen , Seungwon Jeon , Jaehoon Chung , Arnd Bergmann , Olof Johansson , Pavel Machek , Subject: [PATCH 5/5] mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGA Date: Tue, 14 May 2013 17:52:35 -0500 Message-ID: <1368571955-6652-5-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368571955-6652-1-git-send-email-dinguyen@altera.com> References: <1368571955-6652-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Dinh Nguyen Add platform specific functionality for the DW SD/MMC driver for SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms can use this define. Signed-off-by: Dinh Nguyen CC: Seungwon Jeon CC: Jaehoon Chung CC: Arnd Bergmann CC: Olof Johansson CC: Pavel Machek CC: linux-mmc@vger.kernel.org --- drivers/mmc/host/Kconfig | 8 +++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/dw_mmc-exynos.c | 2 - drivers/mmc/host/dw_mmc-socfpga.c | 141 +++++++++++++++++++++++++++++++++++++ drivers/mmc/host/dw_mmc.h | 1 + 5 files changed, 151 insertions(+), 2 deletions(-) create mode 100644 drivers/mmc/host/dw_mmc-socfpga.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 9ab8f8d..1be2289 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -556,6 +556,14 @@ config MMC_DW_EXYNOS Synopsys DesignWare Memory Card Interface driver. Select this option for platforms based on Exynos4 and Exynos5 SoC's. +config MMC_DW_SOCFPGA + tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface" + depends on MMC_DW + select MMC_DW_PLTFM + help + This selects support for Altera SoCFPGA specific extensions to the + Synopsys DesignWare Memory Card Interface driver. + config MMC_DW_PCI tristate "Synopsys Designware MCI support on PCI bus" depends on MMC_DW && PCI diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index cd32280..67718c1 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o obj-$(CONFIG_MMC_DW) += dw_mmc.o obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o +obj-$(CONFIG_MMC_DW_SOCFPGA) += dw_mmc-socfpga.o obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index f013e7e..866edef 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -31,8 +31,6 @@ SDMMC_CLKSEL_CCLK_DRIVE(y) | \ SDMMC_CLKSEL_CCLK_DIVIDER(z)) -#define SDMMC_CMD_USE_HOLD_REG BIT(29) - #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c new file mode 100644 index 0000000..7eb3163 --- /dev/null +++ b/drivers/mmc/host/dw_mmc-socfpga.c @@ -0,0 +1,141 @@ +/* + * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface driver + * + * Copyright (C) 2012, Samsung Electronics Co., Ltd. + * Copyright (C) 2013 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Taken from dw_mmc_exynos.c + */ +#include +#include +#include +#include +#include +#include + +#include "dw_mmc.h" +#include "dw_mmc-pltfm.h" + +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 +#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + +extern void __iomem *sys_manager_base_addr; + +/* SOCFPGA implementation specific driver private data */ +struct dw_mci_socfpga_priv_data { + u8 ciu_div; + u32 hs_timing; +}; + +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct dw_mci_socfpga_priv_data *priv; + struct device *dev = host->dev; + int pwr_en; + + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(host->dev, "mem alloc failed for private data\n"); + return -ENOMEM; + } + + host->priv = priv; + + if (of_property_read_u32(dev->of_node, "pwr-en", &pwr_en)) { + dev_info(dev, "couldn't determine pwr-en, assuming pwr-en = 0\n"); + pwr_en = 0; + } + + /* Set PWREN bit */ + mci_writel(host, PWREN, pwr_en); + + return 0; +} + +static int dw_mci_socfpga_setup_clock(struct dw_mci *host) +{ + struct dw_mci_socfpga_priv_data *priv = host->priv; + + clk_disable(host->ciu_clk); + writel(priv->hs_timing, sys_manager_base_addr + + SYSMGR_SDMMCGRP_CTRL_OFFSET); + clk_enable(host->ciu_clk); + + host->bus_hz /= priv->ciu_div; + return 0; +} + +static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr) +{ + struct dw_mci_socfpga_priv_data *priv = host->priv; + + if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK) + *cmdr |= SDMMC_CMD_USE_HOLD_REG; +} + +static int dw_mci_socfpga_parse_dt(struct dw_mci *host) +{ + struct dw_mci_socfpga_priv_data *priv = host->priv; + struct device_node *np = host->dev->of_node; + u32 timing[2]; + u32 div = 0; + int ret; + + of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div); + priv->ciu_div = div; + + ret = of_property_read_u32_array(np, + "altr,dw-mshc-sdr-timing", timing, 2); + if (ret) + return ret; + + priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, + .setup_clock = dw_mci_socfpga_setup_clock, + .prepare_command = dw_mci_socfpga_prepare_command, + .parse_dt = dw_mci_socfpga_parse_dt, +}; + +static const struct of_device_id dw_mci_socfpga_match[] = { + { .compatible = "altr,socfpga-dw-mshc", + .data = &socfpga_drv_data, }, + {}, +}; +MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match); + +int dw_mci_socfpga_probe(struct platform_device *pdev) +{ + const struct dw_mci_drv_data *drv_data; + const struct of_device_id *match; + + match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node); + drv_data = match->data; + return dw_mci_pltfm_register(pdev, drv_data); +} + +static struct platform_driver dw_mci_socfpga_pltfm_driver = { + .probe = dw_mci_socfpga_probe, + .remove = __exit_p(dw_mci_pltfm_remove), + .driver = { + .name = "dwmmc_socfpga", + .of_match_table = of_match_ptr(dw_mci_socfpga_match), + .pm = &dw_mci_pltfm_pmops, + }, +}; + +module_platform_driver(dw_mci_socfpga_pltfm_driver); + +MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:dwmmc-socfpga"); diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 0b74189..3700cb2 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -111,6 +111,7 @@ #define SDMMC_INT_ERROR 0xbfc2 /* Command register defines */ #define SDMMC_CMD_START BIT(31) +#define SDMMC_CMD_USE_HOLD_REG BIT(29) #define SDMMC_CMD_CCS_EXP BIT(23) #define SDMMC_CMD_CEATA_RD BIT(22) #define SDMMC_CMD_UPD_CLK BIT(21)