From patchwork Wed Aug 28 12:08:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2850713 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E779E9F485 for ; Wed, 28 Aug 2013 12:09:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C6C8A20444 for ; Wed, 28 Aug 2013 12:09:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9AC5120445 for ; Wed, 28 Aug 2013 12:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754023Ab3H1MJa (ORCPT ); Wed, 28 Aug 2013 08:09:30 -0400 Received: from mail-pb0-f51.google.com ([209.85.160.51]:40564 "EHLO mail-pb0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753908Ab3H1MJa (ORCPT ); Wed, 28 Aug 2013 08:09:30 -0400 Received: by mail-pb0-f51.google.com with SMTP id jt11so6149777pbb.24 for ; Wed, 28 Aug 2013 05:09:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hgrKS/V9ZV/GvYqFZiRVFi9e/GsYQBG3RRdmqMmo6r4=; b=fcNnh6QpnDDCnnhYBFTnTWj144IA2LFdJYToHRK7h3r6s+XES1AZg9kabk08a+8tRJ RU39c7n+68/GE2OHesT8SPokDOZlzM5wTXhu0IWwq02c6Ank63P8Tsd6PjTDuwtGrMH3 if7kEvDaPhgcvH66/O9BDWQIokwGyk2MQLuZHxVQ5kANzAe2jHHhVeCgNtQ6yDh0OC39 MPcQxietjxQFzvJ+HoREiH+OqEcPr60wh3+uMK9iRa+Rad8sq6Y6SuMDhjChuY6Igqx/ ISTAdZYgkGwHxh2du+rEECJNUAAQPyViNKvBtCHzlH9k6ulkHZa0Y3ztDt9dpGG6X1/0 sNEg== X-Received: by 10.68.90.99 with SMTP id bv3mr27103006pbb.108.1377691769689; Wed, 28 Aug 2013 05:09:29 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id fy4sm2986328pbb.1.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 Aug 2013 05:09:28 -0700 (PDT) From: Yuvaraj Kumar C D To: linux-mmc@vger.kernel.org, linux-samsung-soc@vger.kernel.org, cjb@laptop.org, jh80.chung@samsung.com, tgih.jun@samsung.com Cc: ks.giri@samsung.com, t.figa@samsung.com, alim.akhtar@samsung.com, Yuvaraj Kumar C D Subject: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420. Date: Wed, 28 Aug 2013 17:38:51 +0530 Message-Id: <1377691731-7226-5-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377691731-7226-1-git-send-email-yuvaraj.cd@samsung.com> References: <1377691731-7226-1-git-send-email-yuvaraj.cd@samsung.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos5420 Mobile Storage Host controller has Security Management Unit (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures SMU for exynos5420. This patch is on top of the below patch by Doug Anderson. mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT changes since V2: 1.Droppped the bypass-smu quirk. 2.Changed the subject line for this patch add a quirk for SMU -> configure SMU in exynos5420 changes since V1: 1.avoid code duplication by calling dw_mci_exynos_priv_init in resume path. Signed-off-by: Yuvaraj Kumar C D Signed-off-by: Alim Akhtar --- drivers/mmc/host/dw_mmc-exynos.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 19c845b..db28f10 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -35,6 +35,25 @@ #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 +/* Block number in eMMC */ +#define DWMCI_BLOCK_NUM 0xFFFFFFFF + +#define SDMMC_EMMCP_BASE 0x1000 +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) +#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) +#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) + +/* SMU control bits */ +#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7) +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6) +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5) +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) +#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3) +#define DWMCI_MPSCTRL_ECB_MODE BIT(2) +#define DWMCI_MPSCTRL_ENCRYPTION BIT(1) +#define DWMCI_MPSCTRL_VALID BIT(0) + /* Variations in Exynos specific dw-mshc controller */ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS4210, @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) { + mci_writel(host, MPSBEGIN0, 0); + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM); + mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT | + DWMCI_MPSCTRL_NON_SECURE_READ_BIT | + DWMCI_MPSCTRL_VALID | + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT); + } + return 0; } @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev) { struct dw_mci *host = dev_get_drvdata(dev); + dw_mci_exynos_priv_init(host); return dw_mci_resume(host); }