From patchwork Tue Sep 3 09:29:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 2853159 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 216089F3DC for ; Tue, 3 Sep 2013 09:30:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77129201C0 for ; Tue, 3 Sep 2013 09:30:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BC96C201E7 for ; Tue, 3 Sep 2013 09:30:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932691Ab3ICJaO (ORCPT ); Tue, 3 Sep 2013 05:30:14 -0400 Received: from mail-ea0-f181.google.com ([209.85.215.181]:51776 "EHLO mail-ea0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932610Ab3ICJaN (ORCPT ); Tue, 3 Sep 2013 05:30:13 -0400 Received: by mail-ea0-f181.google.com with SMTP id d10so2870359eaj.40 for ; Tue, 03 Sep 2013 02:30:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IZluyq4ybtqtzSarOHxRcGHA/dtzY5CrX6js7960b/Q=; b=FHT93IEMefge7so92g0Z/h5Gj6sgpJZjjq/avK6ZOOzatFFirYg14qnIp2C63oUj96 W3F1Xqc3X0HXRetPQ6EZgLzuJerx7+lVxHVGvAjV4yto2Ek3kCdw+KgGXiBjXroHohtC wOheAJOtKgCVNba1yfej+0YSJC7t1zIVnYvgCLIom/U2oaGBpwEhyoea8YHX3tDjzAZz HP9g0kpVewjj2Omut2Sl/YzekgCEGq7OXujRLXCjtqq6+GGTB7gp9yziTVYGT2ofF+Ox uQnjyKhKD/3y7BQIbocw/mCcHNjH9kwDOUKCKDDueetUhTUByF4XXlx1P2KYXDESDDrL 781w== X-Gm-Message-State: ALoCoQlCYE+s/U0deZfFCOm4b0EqU8e7RXZ3fHQVdFGubAB3I3QqKinEFjk9Ls3/YYe7geFhxWDi X-Received: by 10.14.246.11 with SMTP id p11mr45496537eer.9.1378200612688; Tue, 03 Sep 2013 02:30:12 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id z12sm29882771eev.6.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 02:30:12 -0700 (PDT) From: Ulf Hansson To: linux-arm-kernel@lists.infradead.org, Russell King Cc: linux-mmc@vger.kernel.org, Chris Ball , Daniel Lezcano , Linus Walleij , Ulf Hansson , Johan Rudholm Subject: [PATCH V3 3/4] mmc: mmci: Adapt to register write restrictions Date: Tue, 3 Sep 2013 11:29:35 +0200 Message-Id: <1378200576-13413-4-git-send-email-ulf.hansson@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1378200576-13413-1-git-send-email-ulf.hansson@linaro.org> References: <1378200576-13413-1-git-send-email-ulf.hansson@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After a write to the MMCICLOCK register data cannot be written to this register for three feedback clock cycles. Writes to the MMCIPOWER register must be separated by three MCLK cycles. Previously no issues has been observered, but using higher ARM clock frequencies on STE- platforms has triggered this problem. The MMCICLOCK register is written to in .set_ios and for some data transmissions for SDIO. We do not need a delay at the data transmission path, because sending and receiving data will require more than three clock cycles. Then we use a simple logic to only delay in .set_ios and thus we don't affect throughput performance. Signed-off-by: Johan Rudholm Signed-off-by: Ulf Hansson Acked-by: Rickard Andersson Reviewed-by: Daniel Lezcano --- drivers/mmc/host/mmci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index c550b3e..82afcd3 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -189,6 +189,21 @@ static int mmci_validate_data(struct mmci_host *host, return 0; } +static void mmci_reg_delay(struct mmci_host *host) +{ + /* + * According to the spec, at least three feedback clock cycles + * of max 52 MHz must pass between two writes to the MMCICLOCK reg. + * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. + * Worst delay time during card init is at 100 kHz => 30 us. + * Worst delay time when up and running is at 25 MHz => 120 ns. + */ + if (host->cclk < 20000000) + udelay(30); + else + ndelay(120); +} + /* * This must be called with host->lock held */ @@ -1264,6 +1279,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) mmci_set_clkreg(host, ios->clock); mmci_write_pwrreg(host, pwr); + mmci_reg_delay(host); spin_unlock_irqrestore(&host->lock, flags);