From patchwork Fri Nov 1 09:45:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shen, Jackey" X-Patchwork-Id: 3123651 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 144F19F489 for ; Fri, 1 Nov 2013 09:46:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CAC8E20123 for ; Fri, 1 Nov 2013 09:46:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 467E52047C for ; Fri, 1 Nov 2013 09:46:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754891Ab3KAJqG (ORCPT ); Fri, 1 Nov 2013 05:46:06 -0400 Received: from co9ehsobe001.messaging.microsoft.com ([207.46.163.24]:55886 "EHLO co9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754872Ab3KAJqE (ORCPT ); Fri, 1 Nov 2013 05:46:04 -0400 Received: from mail72-co9-R.bigfish.com (10.236.132.252) by CO9EHSOBE031.bigfish.com (10.236.130.94) with Microsoft SMTP Server id 14.1.225.22; Fri, 1 Nov 2013 09:46:04 +0000 Received: from mail72-co9 (localhost [127.0.0.1]) by mail72-co9-R.bigfish.com (Postfix) with ESMTP id D9B1E1002B1; Fri, 1 Nov 2013 09:46:03 +0000 (UTC) X-Forefront-Antispam-Report: CIP:165.204.84.221; KIP:(null); UIP:(null); IPV:NLI; H:atltwp01.amd.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VPS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah2222h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h1155h) Received: from mail72-co9 (localhost.localdomain [127.0.0.1]) by mail72-co9 (MessageSwitch) id 1383299160120522_26702; Fri, 1 Nov 2013 09:46:00 +0000 (UTC) Received: from CO9EHSMHS006.bigfish.com (unknown [10.236.132.230]) by mail72-co9.bigfish.com (Postfix) with ESMTP id 0ECF4460234; Fri, 1 Nov 2013 09:46:00 +0000 (UTC) Received: from atltwp01.amd.com (165.204.84.221) by CO9EHSMHS006.bigfish.com (10.236.130.16) with Microsoft SMTP Server id 14.16.227.3; Fri, 1 Nov 2013 09:45:59 +0000 X-WSS-ID: 0MVKWGA-07-CGB-02 X-M-MSG: Received: from satlvexedge01.amd.com (satlvexedge01.amd.com [10.177.96.28]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.2.1) with ESMTPS id 2129112C0011; Fri, 1 Nov 2013 04:45:45 -0500 (CDT) Received: from SATLEXDAG04.amd.com (10.181.40.9) by satlvexedge01.amd.com (10.177.96.28) with Microsoft SMTP Server (TLS) id 14.2.328.9; Fri, 1 Nov 2013 04:46:23 -0500 Received: from SCYBEXDAG02.amd.com (10.34.11.12) by satlexdag04.amd.com (10.181.40.9) with Microsoft SMTP Server (TLS) id 14.2.328.9; Fri, 1 Nov 2013 05:45:57 -0400 Received: from ubuntu.amd.com (10.237.74.62) by SCYBEXDAG02.amd.com (10.34.11.12) with Microsoft SMTP Server id 14.2.328.9; Fri, 1 Nov 2013 17:45:56 +0800 From: Jackey Shen To: CC: , , , Jackey Shen Subject: [PATCH] mmc: sdhci: supporting PCI MSI Date: Fri, 1 Nov 2013 17:45:19 +0800 Message-ID: <1383299119-3952-1-git-send-email-Jackey.Shen@amd.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-OriginatorOrg: amd.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable MSI support in sdhci-pci driver and provide the mechanism to fall back to Legacy Pin-based Interrupt if MSI register fails. Signed-off-by: Jackey Shen Reviewed-by: Huang Rui --- drivers/mmc/host/Kconfig | 11 +++++ drivers/mmc/host/sdhci.c | 108 ++++++++++++++++++++++++++++++++++++++++------ include/linux/mmc/sdhci.h | 2 + 3 files changed, 109 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 7fc5099..a56cf27 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -68,6 +68,17 @@ config MMC_SDHCI_PCI If unsure, say N. +config MMC_SDHCI_PCI_MSI + bool "SDHCI support with MSI on PCI bus" + depends on MMC_SDHCI_PCI && PCI_MSI + help + This enables PCI MSI (Message Signaled Interrupts) for Secure + Digital Host Controller Interface. + + If you have a controller with this capability, say Y or M here. + + If unsure, say N. + config MMC_RICOH_MMC bool "Ricoh MMC Controller Disabler" depends on MMC_SDHCI_PCI diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 6785fb1..de509bc 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -13,6 +13,10 @@ * - JMicron (hardware and technical support) */ +#ifdef CONFIG_MMC_SDHCI_PCI_MSI +#include +#endif + #include #include #include @@ -2520,6 +2524,64 @@ out: return result; } +#ifdef CONFIG_MMC_SDHCI_PCI_MSI +static int sdhci_setup_msi(struct sdhci_host *host) +{ + int ret; + struct pci_dev *pdev = to_pci_dev(host->mmc->parent); + + host->msi_enabled = false; + + ret = pci_enable_msi(pdev); + if (ret) { + pr_warn("%s: Failed to allocate MSI entry\n", + mmc_hostname(host->mmc)); + return ret; + } + + ret = request_irq(pdev->irq, sdhci_irq, 0, + mmc_hostname(host->mmc), host); + if (ret) { + pr_warn("%s: Failed to request MSI IRQ %d: %d\n", + mmc_hostname(host->mmc), pdev->irq, ret); + pci_disable_msi(pdev); + return ret; + } + + host->irq = pdev->irq; + host->msi_enabled = true; + return ret; +} + +static int sdhci_try_enable_msi(struct sdhci_host *host) +{ + return sdhci_setup_msi(host); +} + +static void sdhci_cleanup_msi(struct sdhci_host *host) +{ + struct pci_dev *pdev = to_pci_dev(host->mmc->parent); + + free_irq(host->irq, host); + if (host->msi_enabled) { + pci_disable_msi(pdev); + host->msi_enabled = false; + } +} + +#else + +static int sdhci_try_enable_msi(struct sdhci_host *host) +{ + return 0; +} + +static void sdhci_cleanup_msi(struct sdhci_host *host) +{ + free_irq(host->irq, host); +} +#endif /* CONFIG_MMC_SDHCI_PCI_MSI */ + /*****************************************************************************\ * * * Suspend/resume * @@ -2569,7 +2631,8 @@ int sdhci_suspend_host(struct sdhci_host *host) if (!device_may_wakeup(mmc_dev(host->mmc))) { sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); - free_irq(host->irq, host); + /* free any IRQ and disable MSI */ + sdhci_cleanup_msi(host); } else { sdhci_enable_irq_wakeups(host); enable_irq_wake(host->irq); @@ -2589,10 +2652,22 @@ int sdhci_resume_host(struct sdhci_host *host) } if (!device_may_wakeup(mmc_dev(host->mmc))) { - ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, - mmc_hostname(host->mmc), host); + /* try to enable MSI */ + ret = sdhci_try_enable_msi(host); if (ret) - return ret; + pr_warn("%s: Fall back to Legacy Pin-based Interrupt: %d\n", + mmc_hostname(host->mmc), ret); + + if (!host->msi_enabled) { + /* fall back to legacy pin-based interrupt */ + ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, + mmc_hostname(host->mmc), host); + if (ret) { + pr_err("%s: Failed to request IRQ %d: %d\n", + mmc_hostname(host->mmc), host->irq, ret); + return ret; + } + } } else { sdhci_disable_irq_wakeups(host); disable_irq_wake(host->irq); @@ -3212,12 +3287,21 @@ int sdhci_add_host(struct sdhci_host *host) sdhci_init(host, 0); - ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, - mmc_hostname(mmc), host); - if (ret) { - pr_err("%s: Failed to request IRQ %d: %d\n", - mmc_hostname(mmc), host->irq, ret); - goto untasklet; + /* try to enable MSI */ + ret = sdhci_try_enable_msi(host); + if (ret) + pr_warn("%s: Fall back to Legacy Pin-based Interrupt: %d\n", + mmc_hostname(host->mmc), ret); + + if (!host->msi_enabled) { + /* fall back to legacy pin-based interrupt */ + ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, + mmc_hostname(host->mmc), host); + if (ret) { + pr_err("%s: Failed to request IRQ %d: %d\n", + mmc_hostname(host->mmc), host->irq, ret); + goto untasklet; + } } #ifdef CONFIG_MMC_DEBUG @@ -3257,7 +3341,7 @@ int sdhci_add_host(struct sdhci_host *host) reset: sdhci_reset(host, SDHCI_RESET_ALL); sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); - free_irq(host->irq, host); + sdhci_cleanup_msi(host); #endif untasklet: tasklet_kill(&host->card_tasklet); @@ -3300,7 +3384,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) sdhci_reset(host, SDHCI_RESET_ALL); sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); - free_irq(host->irq, host); + sdhci_cleanup_msi(host); del_timer_sync(&host->timer); diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 3e781b8..3812479 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -99,6 +99,8 @@ struct sdhci_host { /* Controller has a non-standard host control register */ #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) + bool msi_enabled; /* SD host controller with PCI MSI enabled */ + int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */