From patchwork Fri Dec 6 16:10:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3298891 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 21CD4C0D4A for ; Fri, 6 Dec 2013 16:12:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6599420523 for ; Fri, 6 Dec 2013 16:12:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 48F0B20439 for ; Fri, 6 Dec 2013 16:12:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756104Ab3LFQMQ (ORCPT ); Fri, 6 Dec 2013 11:12:16 -0500 Received: from va3ehsobe005.messaging.microsoft.com ([216.32.180.31]:14267 "EHLO va3outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753168Ab3LFQMO (ORCPT ); Fri, 6 Dec 2013 11:12:14 -0500 Received: from mail216-va3-R.bigfish.com (10.7.14.234) by VA3EHSOBE010.bigfish.com (10.7.40.12) with Microsoft SMTP Server id 14.1.225.22; Fri, 6 Dec 2013 16:12:13 +0000 Received: from mail216-va3 (localhost [127.0.0.1]) by mail216-va3-R.bigfish.com (Postfix) with ESMTP id 0336D5E019F; Fri, 6 Dec 2013 16:12:13 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received-SPF: pass (mail216-va3: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail216-va3 (localhost.localdomain [127.0.0.1]) by mail216-va3 (MessageSwitch) id 1386346330936961_3584; Fri, 6 Dec 2013 16:12:10 +0000 (UTC) Received: from VA3EHSMHS010.bigfish.com (unknown [10.7.14.241]) by mail216-va3.bigfish.com (Postfix) with ESMTP id D4EB1CC0083; Fri, 6 Dec 2013 16:12:10 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by VA3EHSMHS010.bigfish.com (10.7.99.20) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 6 Dec 2013 16:12:10 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Fri, 6 Dec 2013 08:00:16 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id rB6GC6GO009095; Fri, 6 Dec 2013 08:12:08 -0800 (PST) From: To: , , , , , , , , CC: , Dinh Nguyen Subject: [PATCH 1/2] mmc: dw_mmc: Enable the hold reg for certain speed modes Date: Fri, 6 Dec 2013 10:10:22 -0600 Message-ID: <1386346223-18464-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386346223-18464-1-git-send-email-dinguyen@altera.com> References: <1386346223-18464-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200. According to the Synopsys databook :"To meet the relatively high Input Hold Time requirement for SDR12, SDR25, and other MMC speed modes, you should program bit[29]use_hold_Reg of the CMD register to 1'b1;"..."However, for the higher speed modes of SDR104, SDR50 and DDR50, you can meet the much smaller Input Hold Time requirement of 0.8ns by bypassing the Hold Register (Path A in Figure 10-8, programming CMD.use_hold_reg = 1'b0) and then adding delay elements on the output path as indicated." This information is taking from the v2.50a of the Synopsys Designware Cores Mobile Storage Host Databook. Signed-off-by: Dinh Nguyen --- drivers/mmc/host/dw_mmc.c | 14 ++++++++++++++ include/linux/mmc/dw_mmc.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 4bce0de..7075248 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -279,6 +279,9 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) cmdr |= SDMMC_CMD_DAT_WR; } + if (slot->host->use_hold_reg) + cmdr |= SDMMC_CMD_USE_HOLD_REG; + if (drv_data && drv_data->prepare_command) drv_data->prepare_command(slot->host, &cmdr); @@ -969,6 +972,17 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) mci_writel(slot->host, UHS_REG, regs); slot->host->timing = ios->timing; + switch (slot->host->timing) { + case MMC_TIMING_UHS_SDR50: + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_HS200: + slot->host->use_hold_reg = 0; + break; + default: + slot->host->use_hold_reg = 1; + } + /* * Use mirror of ios->clock to prevent race with mmc * core ios update when finding the minimum. diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h index 6ce7d2c..b9bf3b8 100644 --- a/include/linux/mmc/dw_mmc.h +++ b/include/linux/mmc/dw_mmc.h @@ -191,6 +191,7 @@ struct dw_mci { struct regulator *vmmc; /* Power regulator */ unsigned long irq_flags; /* IRQ flags */ int irq; + bool use_hold_reg; }; /* DMA ops for Internal/External DMAC interface */