From patchwork Thu Dec 12 20:30:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3334311 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2A4F9C0D4A for ; Thu, 12 Dec 2013 21:07:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 030AA207E4 for ; Thu, 12 Dec 2013 21:07:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0822D207D1 for ; Thu, 12 Dec 2013 21:07:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751907Ab3LLVHG (ORCPT ); Thu, 12 Dec 2013 16:07:06 -0500 Received: from va3ehsobe010.messaging.microsoft.com ([216.32.180.30]:3831 "EHLO va3outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751935Ab3LLVG7 (ORCPT ); Thu, 12 Dec 2013 16:06:59 -0500 Received: from mail115-va3-R.bigfish.com (10.7.14.243) by VA3EHSOBE006.bigfish.com (10.7.40.26) with Microsoft SMTP Server id 14.1.225.22; Thu, 12 Dec 2013 21:06:48 +0000 Received: from mail115-va3 (localhost [127.0.0.1]) by mail115-va3-R.bigfish.com (Postfix) with ESMTP id 583ED4001C5; Thu, 12 Dec 2013 21:06:48 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.231; KIP:(null); UIP:(null); IPV:NLI; H:sj-itexedge01.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 11 X-BigFish: VS11(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hz70kz1de098h8275bh1de097h84d07hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h286p1155h) Received-SPF: pass (mail115-va3: domain of altera.com designates 66.35.236.231 as permitted sender) client-ip=66.35.236.231; envelope-from=dinguyen@altera.com; helo=sj-itexedge01.altera.priv.altera.com ; v.altera.com ; Received: from mail115-va3 (localhost.localdomain [127.0.0.1]) by mail115-va3 (MessageSwitch) id 1386882406225027_11826; Thu, 12 Dec 2013 21:06:46 +0000 (UTC) Received: from VA3EHSMHS021.bigfish.com (unknown [10.7.14.229]) by mail115-va3.bigfish.com (Postfix) with ESMTP id 252BA440090; Thu, 12 Dec 2013 21:06:46 +0000 (UTC) Received: from sj-itexedge01.altera.priv.altera.com (66.35.236.231) by VA3EHSMHS021.bigfish.com (10.7.99.31) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 12 Dec 2013 21:06:45 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge01.altera.priv.altera.com (66.35.236.231) with Microsoft SMTP Server id 8.3.298.1; Thu, 12 Dec 2013 12:58:16 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id e063HToP010208; Wed, 5 Jan 2000 19:17:36 -0800 (PST) From: To: , , , , , , , , , , , , , CC: , , , , Dinh Nguyen , Dinh Nguyen Subject: [PATCHv6 2/5] clk: socfpga: Add a clock type for the SD/MMC driver Date: Thu, 12 Dec 2013 14:30:42 -0600 Message-ID: <1386880245-10192-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386880245-10192-1-git-send-email-dinguyen@altera.com> References: <1386880245-10192-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Add a "altr,socfpga-sdmmc-sdr-clk" clock type in the SOCFPGA clock driver. This clock type is not really a "clock" for say, but a mechanism to set the phase shift of the clock that is used to feed the SD/MMC CIU's clock. This clock does not have parent so it is designated as a CLK_IS_ROOT. This clock implements the set_clk_rate method that is meant to receive the SDR settings that is designated by the "samsung,dw-mshc-sdr-timing" binding. The SD/MMC driver passes this clock phase information into the clock driver to use. This enables the SD/MMC driver to touch registers that are located outside of the SD/MMC IP, which helps make the core SD/MMC driver generic. Signed-off-by: Dinh Nguyen --- v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to set the phase shift settings. v5: Use the "snps,dw-mshc" binding v4: Use the sdmmc_clk prepare function to set the phase shift settings v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is loaded after the clock driver. v2: Use the syscon driver --- drivers/clk/socfpga/clk.c | 86 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 280c983..f4c983e 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -21,8 +21,10 @@ #include #include #include +#include #include #include +#include /* Clock Manager offsets */ #define CLKMGR_CTRL 0x0 @@ -69,6 +71,84 @@ struct socfpga_clk { }; #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw) +/* SDMMC Group for System Manager defines */ +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) +struct sdmmc_sdr_clk { + struct clk_hw hw; + u32 reg; +}; +#define to_sdmmc_sdr_clk(p) container_of(p, struct sdmmc_sdr_clk, hw) + +static int sdr_clk_set_rate(struct clk_hw *hwclk, unsigned long rate, + unsigned long parent_rate) +{ + struct sdmmc_sdr_clk *sdmmc_sdr_clk = to_sdmmc_sdr_clk(hwclk); + struct regmap *sys_mgr_base_addr; + u32 hs_timing; + + sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); + if (IS_ERR(sys_mgr_base_addr)) { + pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); + return -EINVAL; + } + hs_timing = SYSMGR_SDMMC_CTRL_SET(((rate > 4) & 0xf), (rate & 0xf)); + regmap_write(sys_mgr_base_addr, sdmmc_sdr_clk->reg, hs_timing); + return 0; +} + +static unsigned long sdr_clk_recalc_rate(struct clk_hw *hwclk, + unsigned long parent_rate) +{ + return parent_rate; +} + +static long sdr_clk_round_rate(struct clk_hw *hwclk, unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + +static const struct clk_ops sdmmc_sdr_clk_ops = { + .recalc_rate = sdr_clk_recalc_rate, + .round_rate = sdr_clk_round_rate, + .set_rate = sdr_clk_set_rate, +}; + +static __init struct clk *socfpga_sdmmc_sdr_clk_init(struct device_node *node, + const struct clk_ops *ops) +{ + u32 reg; + struct clk *clk; + struct sdmmc_sdr_clk *sdmmc_sdr_clk; + const char *clk_name = node->name; + struct clk_init_data init; + int rc; + + rc = of_property_read_u32(node, "reg", ®); + + sdmmc_sdr_clk = kzalloc(sizeof(*sdmmc_sdr_clk), GFP_KERNEL); + if (WARN_ON(!sdmmc_sdr_clk)) + return NULL; + + sdmmc_sdr_clk->reg = reg; + of_property_read_string(node, "clock-output-names", &clk_name); + + init.name = clk_name; + init.ops = ops; + init.flags = CLK_IS_ROOT; + init.num_parents = 0; + sdmmc_sdr_clk->hw.init = &init; + + clk = clk_register(NULL, &sdmmc_sdr_clk->hw); + if (WARN_ON(IS_ERR(clk))) { + kfree(sdmmc_sdr_clk); + return NULL; + } + rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); + return clk; +} + static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { @@ -332,10 +412,16 @@ static void __init socfpga_gate_init(struct device_node *node) socfpga_gate_clk_init(node, &gateclk_ops); } +static void __init socfpga_sdmmc_init(struct device_node *node) +{ + socfpga_sdmmc_sdr_clk_init(node, &sdmmc_sdr_clk_ops); +} + static struct of_device_id socfpga_child_clocks[] = { { .compatible = "altr,socfpga-pll-clock", socfpga_pll_init, }, { .compatible = "altr,socfpga-perip-clk", socfpga_periph_init, }, { .compatible = "altr,socfpga-gate-clk", socfpga_gate_init, }, + { .compatible = "altr,socfpga-sdmmc-sdr-clk", socfpga_sdmmc_init, }, {}, };