From patchwork Mon Feb 17 07:30:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3660401 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A5041BF13A for ; Mon, 17 Feb 2014 07:33:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 59E09201FB for ; Mon, 17 Feb 2014 07:33:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6D005201F4 for ; Mon, 17 Feb 2014 07:33:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750930AbaBQHdE (ORCPT ); Mon, 17 Feb 2014 02:33:04 -0500 Received: from mail-bn1bhn0126.outbound.protection.outlook.com ([157.56.111.126]:48669 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750896AbaBQHdE (ORCPT ); Mon, 17 Feb 2014 02:33:04 -0500 Received: from BY2FFO11FD023.protection.gbl (10.1.14.33) by BY2FFO11HUB064.protection.gbl (10.1.15.239) with Microsoft SMTP Server (TLS) id 15.0.868.13; Mon, 17 Feb 2014 07:33:00 +0000 Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by BY2FFO11FD023.mail.protection.outlook.com (10.1.15.212) with Microsoft SMTP Server (TLS) id 15.0.868.13 via Frontend Transport; Mon, 17 Feb 2014 07:32:59 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.342.0; Sun, 16 Feb 2014 23:20:22 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id s1H7WuqR010933; Sun, 16 Feb 2014 23:32:58 -0800 (PST) From: To: CC: , , Dinh Nguyen , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Seungwon Jeon" , Jaehoon Chung , "Chris Ball" Subject: [PATCH 2/3] mmc: dw_mmc: Add support for SOCFPGA's platform specific implementation Date: Mon, 17 Feb 2014 01:30:43 -0600 Message-ID: <1392622244-18015-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392622244-18015-1-git-send-email-dinguyen@altera.com> References: <1392622244-18015-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.232; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019001)(6009001)(189002)(199002)(44976005)(74876001)(6806004)(93916002)(81542001)(79102001)(56776001)(77096001)(74502001)(31966008)(47776003)(95416001)(76482001)(74662001)(80976001)(77982001)(77156001)(80022001)(83322001)(94946001)(19580405001)(19580395003)(47446002)(74706001)(48376002)(50466002)(69226001)(95666001)(36756003)(53806001)(81342001)(74366001)(81686001)(76786001)(20776003)(63696002)(94316002)(54316002)(76796001)(81816001)(59766001)(90146001)(83072002)(85852003)(56816005)(4396001)(86362001)(33646001)(92726001)(51856001)(93516002)(53416003)(85306002)(46102001)(65816001)(86152002)(92566001)(49866001)(47736001)(47976001)(87266001)(87936001)(50986001)(50226001)(89996001)(62966002)(87286001)(93136001)(88136002); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2FFO11HUB064; H:SJ-ITEXEDGE02.altera.priv.altera.com; CLIP:66.35.236.232; FPR:E884CA7B.A0C9136B.671C6347.C0810AF9.2020A; MLV:nspm; InfoDomainNonexisten tMX:1;A:1;LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Forefront-PRVS: 012570D5A0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Like the rockchip, Altera's SOCFPGA platform specific implementation of the dw_mmc driver requires using the HOLD register for SD commands. Signed-off-by: Dinh Nguyen Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Seungwon Jeon Cc: Jaehoon Chung Cc: Chris Ball --- drivers/mmc/host/dw_mmc-pltfm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 5c49656..88047cc 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -34,6 +34,10 @@ static const struct dw_mci_drv_data rockchip_drv_data = { .prepare_command = dw_mci_rockchip_prepare_command, }; +static const struct dw_mci_drv_data socfpga_drv_data = { + .prepare_command = dw_mci_rockchip_prepare_command, +}; + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -92,6 +96,8 @@ static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, { .compatible = "rockchip,rk2928-dw-mshc", .data = &rockchip_drv_data }, + { .compatible = "altr,socfpga-dw-mshc", + .data = &socfpga_drv_data }, {}, }; MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match);