diff mbox

[v10,1/3] mmc: sdhci-msm: Qualcomm SDHCI binding documentation

Message ID 1393961226-25618-2-git-send-email-gdjakov@mm-sol.com (mailing list archive)
State New, archived
Headers show

Commit Message

Georgi Djakov March 4, 2014, 7:27 p.m. UTC
This patch adds the device-tree binding documentation for
Qualcomm SDHCI driver. It contains the differences between
the core properties in mmc.txt and the properties used by
the sdhci-msm driver.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |   63 ++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt

Comments

Ulf Hansson March 5, 2014, 4:25 a.m. UTC | #1
On 4 March 2014 20:27, Georgi Djakov <gdjakov@mm-sol.com> wrote:
> This patch adds the device-tree binding documentation for
> Qualcomm SDHCI driver. It contains the differences between
> the core properties in mmc.txt and the properties used by
> the sdhci-msm driver.
>
> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
> ---
>  .../devicetree/bindings/mmc/sdhci-msm.txt          |   63 ++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> new file mode 100644
> index 0000000..c635c53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> @@ -0,0 +1,63 @@
> +* Qualcomm SDHCI controller (sdhci-msm)
> +
> +This file documents differences between the core properties in mmc.txt
> +and the properties used by the sdhci-msm driver.
> +
> +Required properties:
> +- compatible: Should contain "qcom,sdhci-msm-v4".
> +- reg: Base address and length of the register set listed in reg-names.
> +- reg-names: Should contain the following:
> +       "hc_mem"   - Host controller register map
> +       "core_mem" - SD Core register map
> +- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names.
> +- interrupt-names: Should contain the following:
> +       "hc_irq"     - Host controller interrupt
> +       "pwr_irq"    - PMIC interrupt
> +- vdd-supply: Phandle to the regulator for the vdd (core voltage) supply.
> +- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage) supply.

The common naming of the above regulators are "vmmc" and "vqmmc". Is
there any specific reason to why you can't use these names?

Kind regards
Ulf Hansson

> +- pinctrl-names: Should contain only one value - "default".
> +- pinctrl-0: Should specify pin control groups used for this controller.
> +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
> +- clock-names: Should contain the following:
> +       "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
> +       "core"  - SDC MMC clock (MCLK) (required)
> +       "bus"   - SDCC bus voter clock (optional)
> +
> +Example:
> +
> +       sdhc_1: sdhci@f9824900 {
> +               compatible = "qcom,sdhci-msm-v4";
> +               reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
> +               reg-names = "hc_mem", "core_mem";
> +               interrupts = <0 123 0>, <0 138 0>;
> +               interrupt-names = "hc_irq", "pwr_irq";
> +               bus-width = <8>;
> +               non-removable;
> +
> +               vdd-supply = <&pm8941_l20>;
> +               vdd-io-supply = <&pm8941_s3>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
> +
> +               clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
> +               clock-names = "core", "iface";
> +       };
> +
> +       sdhc_2: sdhci@f98a4900 {
> +               compatible = "qcom,sdhci-msm-v4";
> +               reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
> +               reg-names = "hc_mem", "core_mem";
> +               interrupts = <0 125 0>, <0 221 0>;
> +               interrupt-names = "hc_irq", "pwr_irq";
> +               bus-width = <4>;
> +
> +               vdd-supply = <&pm8941_l21>;
> +               vdd-io-supply = <&pm8941_l13>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
> +
> +               clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
> +               clock-names = "core", "iface";
> +       };
> --
> 1.7.9.5
>
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Rob Herring March 5, 2014, 6:56 a.m. UTC | #2
On Tue, Mar 4, 2014 at 1:27 PM, Georgi Djakov <gdjakov@mm-sol.com> wrote:
> This patch adds the device-tree binding documentation for
> Qualcomm SDHCI driver. It contains the differences between
> the core properties in mmc.txt and the properties used by
> the sdhci-msm driver.
>
> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
> ---
>  .../devicetree/bindings/mmc/sdhci-msm.txt          |   63 ++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> new file mode 100644
> index 0000000..c635c53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> @@ -0,0 +1,63 @@
> +* Qualcomm SDHCI controller (sdhci-msm)
> +
> +This file documents differences between the core properties in mmc.txt
> +and the properties used by the sdhci-msm driver.
> +
> +Required properties:
> +- compatible: Should contain "qcom,sdhci-msm-v4".
> +- reg: Base address and length of the register set listed in reg-names.
> +- reg-names: Should contain the following:
> +       "hc_mem"   - Host controller register map
> +       "core_mem" - SD Core register map

reg-names should not be required and the order specified by the binding.

> +- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names.
> +- interrupt-names: Should contain the following:
> +       "hc_irq"     - Host controller interrupt
> +       "pwr_irq"    - PMIC interrupt

Same for interrupt-names.

> +- vdd-supply: Phandle to the regulator for the vdd (core voltage) supply.
> +- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage) supply.
> +- pinctrl-names: Should contain only one value - "default".
> +- pinctrl-0: Should specify pin control groups used for this controller.
> +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
> +- clock-names: Should contain the following:
> +       "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
> +       "core"  - SDC MMC clock (MCLK) (required)
> +       "bus"   - SDCC bus voter clock (optional)
> +
> +Example:
> +
> +       sdhc_1: sdhci@f9824900 {
> +               compatible = "qcom,sdhci-msm-v4";
> +               reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;

Are there cases where these are really in a different 4KB range? If
not, this should just be 1 range.

> +               reg-names = "hc_mem", "core_mem";
> +               interrupts = <0 123 0>, <0 138 0>;
> +               interrupt-names = "hc_irq", "pwr_irq";
> +               bus-width = <8>;
> +               non-removable;
> +
> +               vdd-supply = <&pm8941_l20>;
> +               vdd-io-supply = <&pm8941_s3>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
> +
> +               clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
> +               clock-names = "core", "iface";
> +       };
> +
> +       sdhc_2: sdhci@f98a4900 {
> +               compatible = "qcom,sdhci-msm-v4";
> +               reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
> +               reg-names = "hc_mem", "core_mem";
> +               interrupts = <0 125 0>, <0 221 0>;
> +               interrupt-names = "hc_irq", "pwr_irq";
> +               bus-width = <4>;
> +
> +               vdd-supply = <&pm8941_l21>;
> +               vdd-io-supply = <&pm8941_l13>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
> +
> +               clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
> +               clock-names = "core", "iface";
> +       };
> --
> 1.7.9.5
>
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Georgi Djakov March 5, 2014, 8:21 p.m. UTC | #3
On 03/05/2014 06:25 AM, Ulf Hansson wrote:
> On 4 March 2014 20:27, Georgi Djakov <gdjakov@mm-sol.com> wrote:
[..]
>> +Required properties:
>> +- compatible: Should contain "qcom,sdhci-msm-v4".
>> +- reg: Base address and length of the register set listed in reg-names.
>> +- reg-names: Should contain the following:
>> +       "hc_mem"   - Host controller register map
>> +       "core_mem" - SD Core register map
>> +- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names.
>> +- interrupt-names: Should contain the following:
>> +       "hc_irq"     - Host controller interrupt
>> +       "pwr_irq"    - PMIC interrupt
>> +- vdd-supply: Phandle to the regulator for the vdd (core voltage) supply.
>> +- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage) supply.
>
> The common naming of the above regulators are "vmmc" and "vqmmc". Is
> there any specific reason to why you can't use these names?

Hi Ulf,
They are named this way on the schematics, i will change them to the 
common names. Thanks!

BR,
Georgi
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Josh Cartwright March 5, 2014, 10:10 p.m. UTC | #4
Hey Rob-

On Wed, Mar 05, 2014 at 12:56:22AM -0600, Rob Herring wrote:
> On Tue, Mar 4, 2014 at 1:27 PM, Georgi Djakov <gdjakov@mm-sol.com> wrote:
> > +- reg-names: Should contain the following:
> > +       "hc_mem"   - Host controller register map
> > +       "core_mem" - SD Core register map
>
> reg-names should not be required and the order specified by the binding.
>
> > +- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names.
> > +- interrupt-names: Should contain the following:
> > +       "hc_irq"     - Host controller interrupt
> > +       "pwr_irq"    - PMIC interrupt
>
> Same for interrupt-names.

Could you elaborate on this a bit?  I can understand not modifying an
existing binding to make {reg,interrupt}-names required, but for
completely new bindings, why is this a problem?

Not allowing a binding to require these properties renders
platform_get_{resource,irq}_byname() useless for drivers which
exclusively use DT for enumeration.  It also makes it impossible to make
a reg entry optional (although, there probably isn't a good usecase for
this).

Thanks,
  Josh
Georgi Djakov March 6, 2014, 5:45 p.m. UTC | #5
On 03/05/2014 08:56 AM, Rob Herring wrote:
> On Tue, Mar 4, 2014 at 1:27 PM, Georgi Djakov <gdjakov@mm-sol.com> wrote:
[..]
>> +Required properties:
>> +- compatible: Should contain "qcom,sdhci-msm-v4".
>> +- reg: Base address and length of the register set listed in reg-names.
>> +- reg-names: Should contain the following:
>> +       "hc_mem"   - Host controller register map
>> +       "core_mem" - SD Core register map
>
> reg-names should not be required and the order specified by the binding.
>

Ok, Rob! Thanks!

>> +- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names.
>> +- interrupt-names: Should contain the following:
>> +       "hc_irq"     - Host controller interrupt
>> +       "pwr_irq"    - PMIC interrupt
>
> Same for interrupt-names.
>

Ok.

>> +- vdd-supply: Phandle to the regulator for the vdd (core voltage) supply.
>> +- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage) supply.
>> +- pinctrl-names: Should contain only one value - "default".
>> +- pinctrl-0: Should specify pin control groups used for this controller.
>> +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
>> +- clock-names: Should contain the following:
>> +       "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
>> +       "core"  - SDC MMC clock (MCLK) (required)
>> +       "bus"   - SDCC bus voter clock (optional)
>> +
>> +Example:
>> +
>> +       sdhc_1: sdhci@f9824900 {
>> +               compatible = "qcom,sdhci-msm-v4";
>> +               reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
>
> Are there cases where these are really in a different 4KB range? If
> not, this should just be 1 range.
>

Thanks for your suggestion. This sounds reasonable, but in this case,
I think that it might be better leaving the memory regions separated as 
it will help avoiding code duplication. I am using the generic 
sdhci_pltfm_init(), which assumes that the first resource is the HC 
iomem and configures the host. If I merge them, the HC address will be 
offset and this might require duplicating some of the init code.
Is it acceptable to leave it this way?

BR,
Georgi
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
new file mode 100644
index 0000000..c635c53
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -0,0 +1,63 @@ 
+* Qualcomm SDHCI controller (sdhci-msm)
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-msm driver.
+
+Required properties:
+- compatible: Should contain "qcom,sdhci-msm-v4".
+- reg: Base address and length of the register set listed in reg-names.
+- reg-names: Should contain the following:
+	"hc_mem"   - Host controller register map
+	"core_mem" - SD Core register map
+- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names.
+- interrupt-names: Should contain the following:
+	"hc_irq"     - Host controller interrupt
+	"pwr_irq"    - PMIC interrupt
+- vdd-supply: Phandle to the regulator for the vdd (core voltage) supply.
+- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage) supply.
+- pinctrl-names: Should contain only one value - "default".
+- pinctrl-0: Should specify pin control groups used for this controller.
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
+- clock-names: Should contain the following:
+	"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
+	"core"	- SDC MMC clock (MCLK) (required)
+	"bus"	- SDCC bus voter clock (optional)
+
+Example:
+
+	sdhc_1: sdhci@f9824900 {
+		compatible = "qcom,sdhci-msm-v4";
+		reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+		reg-names = "hc_mem", "core_mem";
+		interrupts = <0 123 0>, <0 138 0>;
+		interrupt-names = "hc_irq", "pwr_irq";
+		bus-width = <8>;
+		non-removable;
+
+		vdd-supply = <&pm8941_l20>;
+		vdd-io-supply = <&pm8941_s3>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
+
+		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
+		clock-names = "core", "iface";
+	};
+
+	sdhc_2: sdhci@f98a4900 {
+		compatible = "qcom,sdhci-msm-v4";
+		reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+		reg-names = "hc_mem", "core_mem";
+		interrupts = <0 125 0>, <0 221 0>;
+		interrupt-names = "hc_irq", "pwr_irq";
+		bus-width = <4>;
+
+		vdd-supply = <&pm8941_l21>;
+		vdd-io-supply = <&pm8941_l13>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
+
+		clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
+		clock-names = "core", "iface";
+	};