[v10,02/15] clk: sunxi: Implement MMC phase control

Commit Message

Hans de Goede May 2, 2014, 3:57 p.m. UTC

From: Emilio López <[e-mail]>

HdG: add header exporting clk_sunxi_mmc_phase_control

Signed-off-by: Emilio López <[e-mail]>
Signed-off-by: Hans de Goede <[e-mail]>
---
 drivers/clk/sunxi/clk-sunxi.c | 36 ++++++++++++++++++++++++++++++++++++
 include/linux/clk/sunxi.h     | 22 ++++++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 include/linux/clk/sunxi.h

Comments

Maxime Ripard May 6, 2014, 6:53 p.m. UTC | #1

Hi Mike,

On Fri, May 02, 2014 at 05:57:16PM +0200, Hans de Goede wrote:
> From: Emilio López <[e-mail]>
> 
> HdG: add header exporting clk_sunxi_mmc_phase_control
> 
> Signed-off-by: Emilio López <[e-mail]>
> Signed-off-by: Hans de Goede <[e-mail]>

Do you agree with Hans proposal to merge this, and then convert to the
clk_set_phase proposal whenever we will have the details of the phase
values?

Thanks,
Maxime

Patch

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index bd7dc73..59f9040 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -507,6 +507,42 @@  CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
 
 
 /**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
+{
+	#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+	#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+	struct clk_composite *composite = to_clk_composite(hw);
+	struct clk_hw *rate_hw = composite->rate_hw;
+	struct clk_factors *factors = to_clk_factors(rate_hw);
+	unsigned long flags = 0;
+	u32 reg;
+
+	if (factors->lock)
+		spin_lock_irqsave(factors->lock, flags);
+
+	reg = readl(factors->reg);
+
+	/* set sample clock phase control */
+	reg &= ~(0x7 << 20);
+	reg |= ((sample & 0x7) << 20);
+
+	/* set output clock phase control */
+	reg &= ~(0x7 << 8);
+	reg |= ((output & 0x7) << 8);
+
+	writel(reg, factors->reg);
+
+	if (factors->lock)
+		spin_unlock_irqrestore(factors->lock, flags);
+}
+EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
+
+
+/**
  * sunxi_factors_clk_setup() - Setup function for factor clocks
  */
 
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 0000000..1ef5c89
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@ 
+/*
+ * Copyright 2013 - Hans de Goede <[e-mail]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+#include <linux/clk.h>
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
+
+#endif