From patchwork Thu May 22 15:18:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 4223771 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 189F29F23C for ; Thu, 22 May 2014 15:20:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4C9DE2037A for ; Thu, 22 May 2014 15:20:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8442520379 for ; Thu, 22 May 2014 15:20:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752327AbaEVPUX (ORCPT ); Thu, 22 May 2014 11:20:23 -0400 Received: from mail-wi0-f178.google.com ([209.85.212.178]:62927 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752015AbaEVPSs (ORCPT ); Thu, 22 May 2014 11:18:48 -0400 Received: by mail-wi0-f178.google.com with SMTP id cc10so4490962wib.17 for ; Thu, 22 May 2014 08:18:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ipIoO9h1W15mYPJ8Cy9AL8yaX11ClbV7FxlhHGdnihI=; b=MH62IxhYqfjqk0q7MP+CLlfdJW1DtdKF8LMtjRjPH1VbLvxhfLevuPdVrwysXlSXmZ gwFWiE2vFdQ6cHN2z7pNwXh5Q/4U5itCim+BkGlL5r7D5CTdIeOr3VESQPIvupuUVvKe wXc6PaaDS5Sonvi5/Ppo4+2w+k2sSg381ZCzxQELJ3TuNuxLLP608nQnWRl0piMQIo+f W8v4uqiGHyr5/OGqPJ+MNh25lIjoj7g0txFt2335YKv6b5u49b08AWpTnULcV5Z7p6ah O4rcuznvseDMJryDDsVpfmEYzTNk0O7T9kJ0AAAf8gUbBES1p4QQVQFau9FmL1+X60s8 l6Hg== X-Gm-Message-State: ALoCoQmqQcKO3TiVAEWhXcacpjNTbqvzuX2S6nmvmO7/3mCyJV0zBBp01VypEUpHOZfnPgfVwxNp X-Received: by 10.194.71.164 with SMTP id w4mr51464888wju.0.1400771926861; Thu, 22 May 2014 08:18:46 -0700 (PDT) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by mx.google.com with ESMTPSA id dk4sm848205wib.14.2014.05.22.08.18.45 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 May 2014 08:18:46 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com, chris@printf.net, ulf.hansson@linaro.org Cc: peter.griffin@linaro.org, kernel@stlinux.com, lee.jones@linaro.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Giuseppe Cavallaro Subject: [PATCH 3/8] ARM: STi: DT: Add sdhci pins for stih416 Date: Thu, 22 May 2014 16:18:17 +0100 Message-Id: <1400771902-26553-4-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400771902-26553-1-git-send-email-peter.griffin@linaro.org> References: <1400771902-26553-1-git-send-email-peter.griffin@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the required pin config for both SDHCI controllers on the stih416 SoC. Signed-off-by: Peter Griffin Signed-off-by: Giuseppe Cavallaro Acked-by: Maxime Coquelin Acked-by: Lee Jones --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 6252188..140af6b 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -467,6 +467,45 @@ }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&PIO15 3 ALT4 IN>; + data4 = <&PIO16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&PIO16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&PIO17 1 ALT4 OUT>; + cd = <&PIO17 2 ALT4 IN>; + led = <&PIO17 3 ALT4 OUT>; + }; + }; + }; + mmc1 { + pinctrl_mmc1: mmc1 { + st,pins { + mmcclk = <&PIO15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO13 7 ALT3 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 1 ALT3 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 2 ALT3 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 3 ALT3 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 4 ALT3 BIDIR_PU BYPASS 0>; + data4 = <&PIO15 6 ALT3 BIDIR_PU BYPASS 0>; + data5 = <&PIO15 7 ALT3 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 0 ALT3 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 1 ALT3 BIDIR_PU BYPASS 0>; + pwr = <&PIO16 2 ALT3 OUT>; + nreset = <&PIO13 6 ALT3 OUT>; + }; + }; + }; }; pin-controller-fvdp-fe {