From patchwork Thu May 22 15:55:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 4224091 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 61FAA9F23C for ; Thu, 22 May 2014 15:55:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7E81A2037D for ; Thu, 22 May 2014 15:55:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A0CDC202C8 for ; Thu, 22 May 2014 15:55:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752080AbaEVPzp (ORCPT ); Thu, 22 May 2014 11:55:45 -0400 Received: from mail-ob0-f201.google.com ([209.85.214.201]:55752 "EHLO mail-ob0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751537AbaEVPzo (ORCPT ); Thu, 22 May 2014 11:55:44 -0400 Received: by mail-ob0-f201.google.com with SMTP id wn1so752466obc.0 for ; Thu, 22 May 2014 08:55:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zUpEC5vohqNwWssCa2GxNNMSxwvytaPyJ6iwe6XMzg8=; b=h4S9F0bHYD2cyVPBnClzYpx77pVf5JBk+8wECg3RTbcd3Cja6cef3feLJfDFGW+pnJ DaVK6ZvSfugEfUgqoUBaiDC18kPmlxwdSEeu5E/DVccEEmDicw0O9/OnlXuKoTXeGi1v H/eI6cOdXKJOgTDm8DFIpkG3hIAdipGxfC6YFngI09mKNf9MRKtRUyLO89GppeXnie8M ih72xABTxw8exhvYUG/K87+qVIYdezfUNkGCMou1+Q5Lr5OukxArFOyPMgZ/jEhIzdnU tVg7/KoCGGawdIDYXHvRTrZtXUvzOn6CjDpnirCWdioRcuueeefWl70I9k1/B/4+L7BD KzyA== X-Gm-Message-State: ALoCoQkIZqo3BpBg5gxbQJDIr90Ack7MHKS4hwN5EHpMiY/fBjwUsqUC+M1e7vamh4cJHqdj13jV X-Received: by 10.42.236.68 with SMTP id kj4mr22695800icb.6.1400774144300; Thu, 22 May 2014 08:55:44 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id n68si13903yhj.5.2014.05.22.08.55.44 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 May 2014 08:55:44 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 2641931C1F3; Thu, 22 May 2014 08:55:44 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id DFCE52209D9; Thu, 22 May 2014 08:55:43 -0700 (PDT) From: Andrew Bresticker To: Chris Ball , Ulf Hansson , Stephen Warren , Thierry Reding Cc: linux-mmc@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Bresticker Subject: [PATCH v3 2/2] mmc: tegra: fix reporting of base clock frequency Date: Thu, 22 May 2014 08:55:36 -0700 Message-Id: <1400774136-12396-2-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1400774136-12396-1-git-send-email-abrestic@chromium.org> References: <1400774136-12396-1-git-send-email-abrestic@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SDHCI controllers, by default, report a base clock frequency of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual base clock frequency. This is because the clock rate is configured by the clock controller, which is external to the SD/MMC controller. Since the SD/MMC controller has no knowledge of how this clock is configured, it will simply report the maximum frequency. While the reported value can be overridden by setting BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set CAP_CLOCK_BASE_BROKEN and supply sdhci_pltfm_clk_get_max_clock(), which simply does a clk_get_rate(), as the get_max_clock() callback. Signed-off-by: Andrew Bresticker Tested-by: Stephen Warren Acked-by: Stephen Warren Signed-off-by: Ulf Hansson --- Changes from v2: - rebased on mmc-next Changes from v1: - fixed up commit message per Stephen's suggestions --- drivers/mmc/host/sdhci-tegra.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 4375cd4..d93a063 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -154,13 +154,15 @@ static const struct sdhci_ops tegra_sdhci_ops = { .set_bus_width = tegra_sdhci_set_bus_width, .reset = tegra_sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, }; static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -175,7 +177,8 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -191,7 +194,8 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, };