From patchwork Wed Jun 4 16:30:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 4295781 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1E7BDBEEA7 for ; Wed, 4 Jun 2014 16:33:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 56095201B9 for ; Wed, 4 Jun 2014 16:33:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C57F1201CE for ; Wed, 4 Jun 2014 16:33:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751901AbaFDQdy (ORCPT ); Wed, 4 Jun 2014 12:33:54 -0400 Received: from mail-we0-f180.google.com ([74.125.82.180]:54458 "EHLO mail-we0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754118AbaFDQbO (ORCPT ); Wed, 4 Jun 2014 12:31:14 -0400 Received: by mail-we0-f180.google.com with SMTP id q58so8785731wes.39 for ; Wed, 04 Jun 2014 09:31:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aZ0JORrVuieFN7oaZJuwCuuSHvMltaLrC0XKFbUWxBE=; b=lJ5WpuUZupi6agN9KBpmEEmG1obPYtx3hWBgqyPfiz80GzOJLBQt1dkTDiaoHS5Xsu +2BnA/LUL6LxkgLylGT/ZZ9vFhLuQ4NYYSP1A4cY9EPy4mcYprYj013H6MwzxcKph657 7Pwak0sqX+/6NaMSNPcCX+Y69USXmWAaXExbCwXDGMiz+GXmgVA4na3FvR1dd0Lj2bxF cqBClY8ZeCiGr/tQydZEdzG9vztlzc3m9Q4mEO/sd+6vaINEUE/nxplLIgPHbpyqwkKk qwHyuqJGxb6oF1+saeZKBiWYfGFDUiqhrUB39OIUFq4d2Leoh/pJbbe9g1CEaQ+n+6uE JhpQ== X-Gm-Message-State: ALoCoQnHGuHS7JBO0SO8ux9PFLqq7diVNkjTklBL5qhwO3MOlftDN+FWZ8dvMIAEsSWU+lLLqx5N X-Received: by 10.194.186.210 with SMTP id fm18mr6624589wjc.67.1401899472822; Wed, 04 Jun 2014 09:31:12 -0700 (PDT) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by mx.google.com with ESMTPSA id s10sm4355698wjs.29.2014.06.04.09.31.11 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jun 2014 09:31:12 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chris@printf.net, ulf.hansson@linaro.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, kernel@stlinux.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Giuseppe Cavallaro Subject: [PATCH v3 03/10] ARM: STi: DT: Add sdhci pins for stih416 Date: Wed, 4 Jun 2014 17:30:17 +0100 Message-Id: <1401899424-1365-4-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401899424-1365-1-git-send-email-peter.griffin@linaro.org> References: <1401899424-1365-1-git-send-email-peter.griffin@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the required pin config for both SDHCI controllers on the stih416 SoC. Signed-off-by: Giuseppe Cavallaro Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 6252188..dad1f24 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -467,6 +467,45 @@ }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&PIO15 3 ALT4 IN>; + data4 = <&PIO16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&PIO16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&PIO17 1 ALT4 OUT>; + cd = <&PIO17 2 ALT4 IN>; + led = <&PIO17 3 ALT4 OUT>; + }; + }; + }; + mmc1 { + pinctrl_mmc1: mmc1 { + st,pins { + mmcclk = <&PIO15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO13 7 ALT3 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 1 ALT3 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 2 ALT3 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 3 ALT3 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 4 ALT3 BIDIR_PU BYPASS 0>; + data4 = <&PIO15 6 ALT3 BIDIR_PU BYPASS 0>; + data5 = <&PIO15 7 ALT3 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 0 ALT3 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 1 ALT3 BIDIR_PU BYPASS 0>; + pwr = <&PIO16 2 ALT3 OUT>; + nreset = <&PIO13 6 ALT3 OUT>; + }; + }; + }; }; pin-controller-fvdp-fe {