From patchwork Wed Jun 4 16:30:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 4295691 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 01B26BEEA7 for ; Wed, 4 Jun 2014 16:32:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3C192201C7 for ; Wed, 4 Jun 2014 16:32:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 63B64201B9 for ; Wed, 4 Jun 2014 16:32:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754210AbaFDQct (ORCPT ); Wed, 4 Jun 2014 12:32:49 -0400 Received: from mail-wg0-f50.google.com ([74.125.82.50]:37597 "EHLO mail-wg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754207AbaFDQbT (ORCPT ); Wed, 4 Jun 2014 12:31:19 -0400 Received: by mail-wg0-f50.google.com with SMTP id x12so8608583wgg.33 for ; Wed, 04 Jun 2014 09:31:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tq2+fHNmlkaMR5jqWGF9ohQdCr8FfMXgWu+CiKm3dLA=; b=j6/1vlp9YOyJh3x3m1y5rH0tGjVUgat/Cs3TXEP42MVcfQnLzT/zJvfbqac1wGpOar qKR5gJRSCB5f0gvBWcQ5h4iX5L0eagsCADqcKmk1xdhCDKlpL9uqMAMXwPs5Ot3s+jRg DnBAHJ3ajt8qqMtNCcbwM/aIUe8l8xMLPXSsZUlqZpbQ+y40f3j6qYM6tH7kLKA7nSX6 BzlrRBhe6Mam9E47BsdL1+19wPpL3DQxK92RqjJWyBjeuKNH+Cj2RtA89NcaK931rnFi Vc5E/n1/Eo3b2bvaVJixqUIfWfbCQuwoJy9I2TNvz2F/LTAAOnp5QkdqxLaJk48MttIs WG1Q== X-Gm-Message-State: ALoCoQmmwSykatGrYNL9Z3cbpPMyFk8Zzx3+nOQRWK31ZddzGAxN6gG5Ci0i4PJKZUkOL6UVy9gK X-Received: by 10.194.91.144 with SMTP id ce16mr72408410wjb.18.1401899477971; Wed, 04 Jun 2014 09:31:17 -0700 (PDT) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by mx.google.com with ESMTPSA id s10sm4355698wjs.29.2014.06.04.09.31.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jun 2014 09:31:17 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chris@printf.net, ulf.hansson@linaro.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, kernel@stlinux.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Giuseppe Cavallaro Subject: [PATCH v3 05/10] ARM: STi: DT: Add sdhci pin configuration for stih415 Date: Wed, 4 Jun 2014 17:30:19 +0100 Message-Id: <1401899424-1365-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401899424-1365-1-git-send-email-peter.griffin@linaro.org> References: <1401899424-1365-1-git-send-email-peter.griffin@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the required pin config for the sdhci controller present in the stih415 SoC. Signed-off-by: Giuseppe Cavallaro Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index caeac7e..eee2373 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -429,6 +429,27 @@ }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&PIO15 3 ALT4 IN>; + data4 = <&PIO16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&PIO16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&PIO17 1 ALT4 OUT>; + cd = <&PIO17 2 ALT4 IN>; + led = <&PIO17 3 ALT4 OUT>; + }; + }; + }; }; pin-controller-left {