From patchwork Wed Jul 9 15:07:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 4516821 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F320BEEAA for ; Wed, 9 Jul 2014 15:13:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 422C02037D for ; Wed, 9 Jul 2014 15:13:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 647942037B for ; Wed, 9 Jul 2014 15:13:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755973AbaGIPNf (ORCPT ); Wed, 9 Jul 2014 11:13:35 -0400 Received: from mail-wi0-f169.google.com ([209.85.212.169]:57912 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932489AbaGIPIH (ORCPT ); Wed, 9 Jul 2014 11:08:07 -0400 Received: by mail-wi0-f169.google.com with SMTP id hi2so2963584wib.4 for ; Wed, 09 Jul 2014 08:08:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3+mqYg2YKlyHfUq4B7or9g6XM9MYWap0ncOXtRclNqc=; b=bX1OnIsibLBdwE65bqmJMWJ5UMjH6e2Cx7t3OByDE/RbYjzZYcuNW9h/G0GGblX8QV 2A5N21IMpPoOI0bGMotctCCsS7hsNPm0JDEQMMzJ8CqiQl4gPOE2BdY/sVLB0oY2QCVS zdFeUuzB9HWeWKroc41dzGqGThqQ0Yuq8Ww9aSWwfKI1Y4B8OF4rfKLR//DGPmdGnQq3 43yRfN+0LeEGPCGnXMna118XnSmPWoNFgRFbJqf1dBig5lR3mRlZLJ1nAqA/vVADyugg gNd3mJnlTot3Wkf+LVy/U8rrf7xB3NDmolOqNhh1E4SbZiAIZ9+KoOAuFxTDYFXtLzVD RYDg== X-Gm-Message-State: ALoCoQmtepmk0kQRgLRdS4qk5F3vcpsTNx93vlgm9Eybc1DenLdnLpKN9dzE2HT00KYOIc5eGzuu X-Received: by 10.194.192.201 with SMTP id hi9mr49517887wjc.28.1404918486690; Wed, 09 Jul 2014 08:08:06 -0700 (PDT) Received: from griffinp-ThinkPad-X1-Carbon-2nd.home (host86-181-29-22.range86-181.btcentralplus.com. [86.181.29.22]) by mx.google.com with ESMTPSA id cd1sm103941088wjc.19.2014.07.09.08.08.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Jul 2014 08:08:06 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ulf.hansson@linaro.org, chris@printf.net, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, peppe.cavallaro@st.com Subject: [PATCH v4 03/10] ARM: STi: DT: Add sdhci pins for stih416 Date: Wed, 9 Jul 2014 16:07:34 +0100 Message-Id: <1404918461-25390-4-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1404918461-25390-1-git-send-email-peter.griffin@linaro.org> References: <1404918461-25390-1-git-send-email-peter.griffin@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the required pin config for both SDHCI controllers on the stih416 SoC. Signed-off-by: Giuseppe Cavallaro Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index ee6c119..01b5ad0 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -467,6 +467,45 @@ }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&PIO15 3 ALT4 IN>; + data4 = <&PIO16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&PIO16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&PIO17 1 ALT4 OUT>; + cd = <&PIO17 2 ALT4 IN>; + led = <&PIO17 3 ALT4 OUT>; + }; + }; + }; + mmc1 { + pinctrl_mmc1: mmc1 { + st,pins { + mmcclk = <&PIO15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO13 7 ALT3 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 1 ALT3 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 2 ALT3 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 3 ALT3 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 4 ALT3 BIDIR_PU BYPASS 0>; + data4 = <&PIO15 6 ALT3 BIDIR_PU BYPASS 0>; + data5 = <&PIO15 7 ALT3 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 0 ALT3 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 1 ALT3 BIDIR_PU BYPASS 0>; + pwr = <&PIO16 2 ALT3 OUT>; + nreset = <&PIO13 6 ALT3 OUT>; + }; + }; + }; }; pin-controller-fvdp-fe {