From patchwork Tue Aug 26 02:50:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Barry Song X-Patchwork-Id: 4777541 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 76A89C0338 for ; Tue, 26 Aug 2014 02:51:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 94E4E201C0 for ; Tue, 26 Aug 2014 02:51:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 92A0C2016C for ; Tue, 26 Aug 2014 02:51:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755563AbaHZCvA (ORCPT ); Mon, 25 Aug 2014 22:51:00 -0400 Received: from cluster-d.mailcontrol.com ([85.115.60.190]:45772 "EHLO cluster-d.mailcontrol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755217AbaHZCvA (ORCPT ); Mon, 25 Aug 2014 22:51:00 -0400 Received: from shaapppus01.asia.root.pri ([210.13.83.99]) by rly08d.srv.mailcontrol.com (MailControl) with ESMTP id s7Q2opgc001765 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Tue, 26 Aug 2014 03:50:54 +0100 Received: from shaasiexc01.ASIA.ROOT.PRI ([10.125.12.102]) by shaapppus01.asia.root.pri (PGP Universal service); Tue, 26 Aug 2014 10:50:55 +0800 X-PGP-Universal: processed; by shaapppus01.asia.root.pri on Tue, 26 Aug 2014 10:50:55 +0800 Received: from barry-laptop.ROOT.PRI (10.125.5.73) by asimail.csr.com (10.125.12.88) with Microsoft SMTP Server (TLS) id 14.3.158.1; Tue, 26 Aug 2014 10:50:50 +0800 From: Barry Song To: , , CC: , , Minda Chen , Barry Song Subject: [PATCH v3] mmc: sdhci-sirf: fix 8bit width enable by overwriting set_bus_width Date: Tue, 26 Aug 2014 10:50:42 +0800 Message-ID: <1409021442-4105-1-git-send-email-Barry.Song@csr.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [10.125.5.73] X-CFilter-Loop: Reflected X-Scanned-By: MailControl 33066.168 (www.mailcontrol.com) on 10.68.0.118 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Minda Chen the implementation of CSR SDHCI controller is a modified version of the one described in the 1.0 specification, and not a normal 3.0 controller. and 8bit-width enable bit of CSR MMC hosts is 3, while stardard hosts use bit 5. this patch fixes the functionality of 8bit transfer in mmc controllers and improve performance for mmc0 a lot. Signed-off-by: Minda Chen Signed-off-by: Barry Song Reviewed-by: Romain Izard --- -v3:fix the HW version check according to Romain's feedback drivers/mmc/host/sdhci-sirf.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c index 1700453..d7b02e5 100644 --- a/drivers/mmc/host/sdhci-sirf.c +++ b/drivers/mmc/host/sdhci-sirf.c @@ -15,6 +15,8 @@ #include #include "sdhci-pltfm.h" +#define SDHCI_SIRF_8BITBUS BIT(3) + struct sdhci_sirf_priv { struct clk *clk; int gpio_cd; @@ -27,10 +29,30 @@ static unsigned int sdhci_sirf_get_max_clk(struct sdhci_host *host) return clk_get_rate(priv->clk); } +static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width) +{ + u8 ctrl; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS); + + /* + * CSR atlas7 and prima2 SD host version is not 3.0 + * 8bit-width enable bit of CSR SD hosts is 3, + * while stardard hosts use bit 5 + */ + if (width == MMC_BUS_WIDTH_8) + ctrl |= SDHCI_SIRF_8BITBUS; + else if (width == MMC_BUS_WIDTH_4) + ctrl |= SDHCI_CTRL_4BITBUS; + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static struct sdhci_ops sdhci_sirf_ops = { .set_clock = sdhci_set_clock, .get_max_clock = sdhci_sirf_get_max_clk, - .set_bus_width = sdhci_set_bus_width, + .set_bus_width = sdhci_sirf_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, };