From patchwork Wed Oct 15 02:01:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Branden X-Patchwork-Id: 5082801 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4E4BB9F30B for ; Wed, 15 Oct 2014 02:02:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 33AD220127 for ; Wed, 15 Oct 2014 02:02:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 16CAA20120 for ; Wed, 15 Oct 2014 02:02:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755915AbaJOCCH (ORCPT ); Tue, 14 Oct 2014 22:02:07 -0400 Received: from mail-gw2-out.broadcom.com ([216.31.210.63]:14648 "EHLO mail-gw2-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755831AbaJOCCB (ORCPT ); Tue, 14 Oct 2014 22:02:01 -0400 X-IronPort-AV: E=Sophos;i="5.04,720,1406617200"; d="scan'208";a="48223748" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw2-out.broadcom.com with ESMTP; 14 Oct 2014 19:23:39 -0700 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 14 Oct 2014 19:02:09 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.174.1; Tue, 14 Oct 2014 19:02:04 -0700 Received: from mail.broadcom.com (lbrmn-lnxub113.ric.broadcom.com [10.136.13.65]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 65EBC40FE6; Tue, 14 Oct 2014 19:01:49 -0700 (PDT) From: Scott Branden To: Stephen Warren , Chris Ball , Ulf Hansson , Russell King , Peter Griffin CC: Ray Jui , , , , , Scott Branden Subject: [PATCH 1/1] mmc: sdhci-bcm2835: added quirk and removed udelay in write ops Date: Tue, 14 Oct 2014 19:01:52 -0700 Message-ID: <1413338512-14546-2-git-send-email-sbranden@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1413338512-14546-1-git-send-email-sbranden@broadcom.com> References: <1413338512-14546-1-git-send-email-sbranden@broadcom.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 present in controller. Removed udelay in write ops by using shadow registers for 16 bit accesses to 32-bit registers (where necessary). Optimized 32-bit operations when doing 8/16 register accesses. Signed-off-by: Scott Branden --- drivers/mmc/host/sdhci-bcm2835.c | 139 ++++++++++++++++++-------------------- 1 file changed, 66 insertions(+), 73 deletions(-) diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c index 439d259..d967a4f 100644 --- a/drivers/mmc/host/sdhci-bcm2835.c +++ b/drivers/mmc/host/sdhci-bcm2835.c @@ -25,42 +25,28 @@ #include "sdhci-pltfm.h" /* - * 400KHz is max freq for card ID etc. Use that as min card clock. We need to - * know the min to enable static calculation of max BCM2835_SDHCI_WRITE_DELAY. - */ -#define MIN_FREQ 400000 - -/* * The Arasan has a bugette whereby it may lose the content of successive - * writes to registers that are within two SD-card clock cycles of each other - * (a clock domain crossing problem). It seems, however, that the data - * register does not have this problem, which is just as well - otherwise we'd - * have to nobble the DMA engine too. + * writes to the same register that are within two SD-card clock cycles of + * each other (a clock domain crossing problem). Problem does not happen with + * data. + * This wouldn't be a problem with the code except that we can only write the + * controller with 32-bit writes. So two different 16-bit registers in the + * written back to back creates the problem. * - * This should probably be dynamically calculated based on the actual card - * frequency. However, this is the longest we'll have to wait, and doesn't - * seem to slow access down too much, so the added complexity doesn't seem - * worth it for now. - * - * 1/MIN_FREQ is (max) time per tick of eMMC clock. - * 2/MIN_FREQ is time for two ticks. - * Multiply by 1000000 to get uS per two ticks. - * *1000000 for uSecs. - * +1 for hack rounding. + * In reality, this only happens when a SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT + * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND. + * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so + * the work around can be further optimized. We can keep shadow values of + * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued. + * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed + * by the TRANSFER+COMMAND in another 32-bit write. */ -#define BCM2835_SDHCI_WRITE_DELAY (((2 * 1000000) / MIN_FREQ) + 1) -struct bcm2835_sdhci { - u32 shadow; +struct bcm2835_sdhci_host { + u32 shadow_cmd; + u32 shadow_blk; }; -static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) -{ - writel(val, host->ioaddr + reg); - - udelay(BCM2835_SDHCI_WRITE_DELAY); -} - static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) { u32 val = readl(host->ioaddr + reg); @@ -71,76 +57,83 @@ static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) return val; } -static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) -{ - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv; - u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow : - bcm2835_sdhci_readl(host, reg & ~3); - u32 word_num = (reg >> 1) & 1; - u32 word_shift = word_num * 16; - u32 mask = 0xffff << word_shift; - u32 newval = (oldval & ~mask) | (val << word_shift); - - if (reg == SDHCI_TRANSFER_MODE) - bcm2835_host->shadow = newval; - else - bcm2835_sdhci_writel(host, newval, reg & ~3); -} - static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) { - u32 val = bcm2835_sdhci_readl(host, (reg & ~3)); - u32 word_num = (reg >> 1) & 1; - u32 word_shift = word_num * 16; - u32 word = (val >> word_shift) & 0xffff; - + u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3)); + u16 word = val >> (reg << 3 & 0x18) & 0xffff; return word; } -static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) +static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) { - u32 oldval = bcm2835_sdhci_readl(host, reg & ~3); - u32 byte_num = reg & 3; - u32 byte_shift = byte_num * 8; - u32 mask = 0xff << byte_shift; - u32 newval = (oldval & ~mask) | (val << byte_shift); + u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3)); + u8 byte = val >> (reg << 3 & 0x18) & 0xff; + return byte; +} - bcm2835_sdhci_writel(host, newval, reg & ~3); +static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) +{ + writel(val, host->ioaddr + reg); } -static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) +static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) { - u32 val = bcm2835_sdhci_readl(host, (reg & ~3)); - u32 byte_num = reg & 3; - u32 byte_shift = byte_num * 8; - u32 byte = (val >> byte_shift) & 0xff; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv; + u32 word_shift = reg << 3 & 0x18; + u32 mask = 0xffff << word_shift; + u32 oldval; + u32 newval; + + if (reg == SDHCI_COMMAND) { + if (bcm2835_host->shadow_blk != 0) { + writel(bcm2835_host->shadow_blk, + host->ioaddr + SDHCI_BLOCK_SIZE); + bcm2835_host->shadow_blk = 0; + } + oldval = bcm2835_host->shadow_cmd; + } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { + oldval = bcm2835_host->shadow_blk; + } else { + oldval = readl(host->ioaddr + (reg & ~3)); + } + newval = (oldval & ~mask) | (val << word_shift); - return byte; + if (reg == SDHCI_TRANSFER_MODE) + bcm2835_host->shadow_cmd = newval; + else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) + bcm2835_host->shadow_blk = newval; + else + writel(newval, host->ioaddr + (reg & ~3)); } -static unsigned int bcm2835_sdhci_get_min_clock(struct sdhci_host *host) +static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) { - return MIN_FREQ; + u32 oldval = readl(host->ioaddr + (reg & ~3)); + u32 byte_shift = reg << 3 & 0x18; + u32 mask = 0xff << byte_shift; + u32 newval = (oldval & ~mask) | (val << byte_shift); + + writel(newval, host->ioaddr + (reg & ~3)); } static const struct sdhci_ops bcm2835_sdhci_ops = { - .write_l = bcm2835_sdhci_writel, - .write_w = bcm2835_sdhci_writew, - .write_b = bcm2835_sdhci_writeb, .read_l = bcm2835_sdhci_readl, .read_w = bcm2835_sdhci_readw, .read_b = bcm2835_sdhci_readb, + .write_l = bcm2835_sdhci_writel, + .write_w = bcm2835_sdhci_writew, + .write_b = bcm2835_sdhci_writeb, .set_clock = sdhci_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, - .get_min_clock = bcm2835_sdhci_get_min_clock, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, }; static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = { - .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | + .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 | + SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, .ops = &bcm2835_sdhci_ops, }; @@ -148,7 +141,7 @@ static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = { static int bcm2835_sdhci_probe(struct platform_device *pdev) { struct sdhci_host *host; - struct bcm2835_sdhci *bcm2835_host; + struct bcm2835_sdhci_host *bcm2835_host; struct sdhci_pltfm_host *pltfm_host; int ret;