From patchwork Thu Feb 26 13:10:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 5892111 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A1CAE9F373 for ; Thu, 26 Feb 2015 13:11:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D1A572039C for ; Thu, 26 Feb 2015 13:11:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E365420382 for ; Thu, 26 Feb 2015 13:11:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932289AbbBZNKq (ORCPT ); Thu, 26 Feb 2015 08:10:46 -0500 Received: from mail-we0-f179.google.com ([74.125.82.179]:35230 "EHLO mail-we0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932263AbbBZNKo (ORCPT ); Thu, 26 Feb 2015 08:10:44 -0500 Received: by wevl61 with SMTP id l61so10569343wev.2 for ; Thu, 26 Feb 2015 05:10:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kDunzBcrBdrAtGCEI7qfUfZnuVf2HH5EYDEMXBpf1Y8=; b=nGruTvQBm8iDcfH3LxZeH5WAEeUI4LJmxhbWvDKF0P7EY4J99xRojOFwSeMDPXe302 ZyoUam7avBdqHru5K6k0ElOQUR4pz9eN9A+9Inq1P7CRjj1x97H/ZJPLIox67rRKlJKL 3JXXzbxHUb0gteQqsIaFPPxPp9Ip0djQ3dNEBKsm/ksW+gmSkM5adYY+ZFHe2InkAVnu A2PjtnSlnh/HUm59faOscWBWFbXjzjmJN2b1QBbK44S9ftxP6ZTzkqHb7LZGsT2i46pD /DOt3jTY+NJe7lNibeKyr5JQ/HqQMlQmqU+fbESz31zUzXM9FG8RLJyn8ffTqYJwM4P9 E6Rw== X-Gm-Message-State: ALoCoQm06nX8jVPoqBNVPyW51b0tKkhqbMtq5fzALl9FT7V1UKuQ+X3Gh93TyzG+otYab2FrfzZ0 X-Received: by 10.180.86.201 with SMTP id r9mr41922495wiz.56.1424956243544; Thu, 26 Feb 2015 05:10:43 -0800 (PST) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by mx.google.com with ESMTPSA id dz6sm23075747wib.0.2015.02.26.05.10.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Feb 2015 05:10:42 -0800 (PST) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com, chris@printf.net, ulf.hansson@linaro.org Cc: peter.griffin@linaro.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, peppe.cavallaro@st.com Subject: [PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function. Date: Thu, 26 Feb 2015 13:10:24 +0000 Message-Id: <1424956227-18258-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424956227-18258-1-git-send-email-peter.griffin@linaro.org> References: <1424956227-18258-1-git-send-email-peter.griffin@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To allow UHS modes to work properly we need to provide the st specific set_uhs_signaling callback function. This function differs from the generic sdhci_set_uhs_signaling callback in that we need to configure the correct delay depending on the UHS mode, and also set the V18_EN bit. Signed-off-by: Peter Griffin Signed-off-by: Giuseppe Cavallaro Acked-by: Maxime Coquelin --- drivers/mmc/host/sdhci-st.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c index 11cf4e2..d53bc82 100644 --- a/drivers/mmc/host/sdhci-st.c +++ b/drivers/mmc/host/sdhci-st.c @@ -260,6 +260,55 @@ static int sdhci_st_set_dll_for_clock(struct sdhci_host *host) return ret; } +static void sdhci_st_set_uhs_signaling(struct sdhci_host *host, + unsigned int uhs) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct st_mmc_platform_data *pdata = pltfm_host->priv; + u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + int ret = 0; + + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (uhs) { + /* + * Set V18_EN -- UHS modes do not work without this. + * does not change signaling voltage + */ + + case MMC_TIMING_UHS_SDR12: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180; + break; + case MMC_TIMING_UHS_SDR25: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180; + break; + case MMC_TIMING_UHS_SDR50: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; + ret = sdhci_st_set_dll_for_clock(host); + break; + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; + ret = sdhci_st_set_dll_for_clock(host); + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; + break; + } + + if (ret) + dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n"); + + dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2); + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} static u32 sdhci_st_readl(struct sdhci_host *host, int reg) { @@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = { .set_bus_width = sdhci_set_bus_width, .read_l = sdhci_st_readl, .reset = sdhci_reset, + .set_uhs_signaling = sdhci_st_set_uhs_signaling, }; static const struct sdhci_pltfm_data sdhci_st_pdata = {