From patchwork Fri Apr 10 08:58:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 6193481 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 314649F1C4 for ; Fri, 10 Apr 2015 09:01:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3E1912037A for ; Fri, 10 Apr 2015 09:01:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 44D792035D for ; Fri, 10 Apr 2015 09:01:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754933AbbDJI65 (ORCPT ); Fri, 10 Apr 2015 04:58:57 -0400 Received: from mail-wi0-f175.google.com ([209.85.212.175]:37541 "EHLO mail-wi0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754805AbbDJI6z (ORCPT ); Fri, 10 Apr 2015 04:58:55 -0400 Received: by wiaa2 with SMTP id a2so18519685wia.0 for ; Fri, 10 Apr 2015 01:58:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2V9CD4KITzU1F0s1DYjsfPNiHgqL6qUOEjCKddEJGrc=; b=YjRip5rRlKg2c2R/DacSGmZX3MQdNycypWghRa5PjCWBaHr8FrbGGu7/KmClXRBpQz OTPOZccAt9Ai84WzbNmTM9Lj2NXxhgaCd3jyEgCDaj9yyPvPtvkRrMfcXjqoikeWieca M9Sf9OfWVGaDu0M71nJAv2+65VC+7rNHbXzx9viX0BGjgPFDsno8SQ0FIH0MTVdhwg5F +H9CmuSHMR/vwCeMPR4ObZiRlTNLxJVROf5CnbKNzgVuzdeVMSvYR7Oa7BmFeqI/hJES +Xpux9yasKc8JumS0wnyv3q2klOqTK7QAlrNA7thgvLdrvlUqEuhfiCQmQ2OUz5c0osm bodw== X-Gm-Message-State: ALoCoQmyevg+7TMFwcBwRlh81pqGrc3PuOB6mdKrIFNYl71dwfsoqgcOnNuy7JNrO5GTSMGa2ea1 X-Received: by 10.180.102.228 with SMTP id fr4mr3006937wib.4.1428656334021; Fri, 10 Apr 2015 01:58:54 -0700 (PDT) Received: from localhost.localdomain ([31.105.225.148]) by mx.google.com with ESMTPSA id ew5sm23844403wic.14.2015.04.10.01.58.51 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Apr 2015 01:58:53 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ulf.hansson@linaro.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, peppe.cavallaro@st.com Subject: [PATCH v4 5/9] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function. Date: Fri, 10 Apr 2015 09:58:27 +0100 Message-Id: <1428656311-2605-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1428656311-2605-1-git-send-email-peter.griffin@linaro.org> References: <1428656311-2605-1-git-send-email-peter.griffin@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To allow UHS modes to work properly we need to provide the st specific set_uhs_signaling callback function. This function differs from the generic sdhci_set_uhs_signaling callback in that we need to configure the correct delay depending on the UHS mode, and also set the V18_EN bit. Signed-off-by: Peter Griffin Signed-off-by: Giuseppe Cavallaro Acked-by: Maxime Coquelin --- drivers/mmc/host/sdhci-st.c | 51 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c index 821be34..2ce842b 100644 --- a/drivers/mmc/host/sdhci-st.c +++ b/drivers/mmc/host/sdhci-st.c @@ -261,6 +261,56 @@ static int sdhci_st_set_dll_for_clock(struct sdhci_host *host) return ret; } +static void sdhci_st_set_uhs_signaling(struct sdhci_host *host, + unsigned int uhs) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct st_mmc_platform_data *pdata = pltfm_host->priv; + u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + int ret = 0; + + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (uhs) { + /* + * Set V18_EN -- UHS modes do not work without this. + * does not change signaling voltage + */ + + case MMC_TIMING_UHS_SDR12: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180; + break; + case MMC_TIMING_UHS_SDR25: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180; + break; + case MMC_TIMING_UHS_SDR50: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; + ret = sdhci_st_set_dll_for_clock(host); + break; + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; + ret = sdhci_st_set_dll_for_clock(host); + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + st_mmcss_set_static_delay(pdata->top_ioaddr); + ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; + break; + } + + if (ret) + dev_warn(mmc_dev(host->mmc), "Error setting dll for clock " + "(uhs %d)\n", uhs); + + dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2); + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} static u32 sdhci_st_readl(struct sdhci_host *host, int reg) { @@ -284,6 +334,7 @@ static const struct sdhci_ops sdhci_st_ops = { .set_bus_width = sdhci_set_bus_width, .read_l = sdhci_st_readl, .reset = sdhci_reset, + .set_uhs_signaling = sdhci_st_set_uhs_signaling, }; static const struct sdhci_pltfm_data sdhci_st_pdata = {