From patchwork Fri Apr 10 13:56:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: dinguyen@opensource.altera.com X-Patchwork-Id: 6197401 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 84AE8BF4A6 for ; Fri, 10 Apr 2015 14:34:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9DA0E203F4 for ; Fri, 10 Apr 2015 14:34:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 435CA203EB for ; Fri, 10 Apr 2015 14:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754934AbbDJOd5 (ORCPT ); Fri, 10 Apr 2015 10:33:57 -0400 Received: from mail-bn1on0099.outbound.protection.outlook.com ([157.56.110.99]:13369 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754770AbbDJOd4 (ORCPT ); Fri, 10 Apr 2015 10:33:56 -0400 X-Greylist: delayed 1938 seconds by postgrey-1.27 at vger.kernel.org; Fri, 10 Apr 2015 10:33:55 EDT Received: from CH1PR03CA002.namprd03.prod.outlook.com (10.255.156.147) by DM2PR0301MB0608.namprd03.prod.outlook.com (0.160.95.24) with Microsoft SMTP Server (TLS) id 15.1.130.23; Fri, 10 Apr 2015 14:01:33 +0000 Received: from BL2FFO11FD051.protection.gbl (10.255.156.132) by CH1PR03CA002.outlook.office365.com (10.255.156.147) with Microsoft SMTP Server (TLS) id 15.1.118.21 via Frontend Transport; Fri, 10 Apr 2015 14:01:33 +0000 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; vger.kernel.org; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of opensource.altera.com does not designate 66.35.236.236 as permitted sender) receiver=protection.outlook.com; client-ip=66.35.236.236; helo=sj-itexedge04.altera.priv.altera.com; Received: from sj-itexedge04.altera.priv.altera.com (66.35.236.236) by BL2FFO11FD051.mail.protection.outlook.com (10.173.161.213) with Microsoft SMTP Server (TLS) id 15.1.136.16 via Frontend Transport; Fri, 10 Apr 2015 14:01:32 +0000 Received: from na01-bn1-obe.outbound.protection.outlook.com (207.46.163.139) by webmail.altera.com (66.35.236.236) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 10 Apr 2015 06:59:13 -0700 Received: from linux-builds1.altera.com (64.129.157.38) by BN3PR03MB1366.namprd03.prod.outlook.com (25.163.34.152) with Microsoft SMTP Server (TLS) id 15.1.118.21; Fri, 10 Apr 2015 14:01:27 +0000 From: To: CC: , , , Dinh Nguyen , Seungwon Jeon , Jaehoon Chung , Chris Ball , Ulf Hansson , Doug Anderson Subject: [PATCH] mmc: dw_mmc: add fixed divider for ciu_clk on SoCFPGA Date: Fri, 10 Apr 2015 08:56:02 -0500 Message-ID: <1428674162-11200-1-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 MIME-Version: 1.0 X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BY2PR06CA033.namprd06.prod.outlook.com (10.141.250.151) To BN3PR03MB1366.namprd03.prod.outlook.com (25.163.34.152) Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:; SRVR:BN3PR03MB1366; UriScan:; BCL:0; PCL:0; RULEID:; SRVR:DM2PR0301MB0608; X-Forefront-Antispam-Report-Untrusted: BMV:1; SFV:NSPM; SFS:(10009020)(6009001)(33646002)(229853001)(46102003)(19580405001)(19580395003)(2351001)(50466002)(48376002)(122386002)(40100003)(92566002)(77156002)(62966003)(50226001)(50986999)(86152002)(87976001)(66066001)(86362001)(53416004)(47776003)(110136001)(42186005); DIR:OUT; SFP:1101; SCL:1; SRVR:BN3PR03MB1366; H:linux-builds1.altera.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:;UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:BN3PR03MB1366; BCL:0; PCL:0; RULEID:; SRVR:BN3PR03MB1366; BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:DM2PR0301MB0608; BCL:0; PCL:0; RULEID:; SRVR:DM2PR0301MB0608; X-Forefront-PRVS: 054231DC40 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1366 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: BL2FFO11FD051.protection.gbl X-Forefront-Antispam-Report: CIP:66.35.236.236; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10009020)(6009001)(339900001)(189002)(199003)(87936001)(50986999)(86362001)(50226001)(19580395003)(19580405001)(47776003)(66066001)(50466002)(6806004)(40100003)(122386002)(46102003)(77156002)(62966003)(105606002)(85426001)(2351001)(92566002)(53416004)(86152002)(16796002)(33646002)(229853001)(48376002)(106466001)(110136001)(7099025); DIR:OUT; SFP:1101; SCL:1; SRVR:DM2PR0301MB0608; H:sj-itexedge04.altera.priv.altera.com; FPR:; SPF:Fail; MLV:ovrnspm; MX:1; A:0; PTR:InfoDomainNonexistent; LANG:en; X-Forefront-PRVS: 054231DC40 X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2015 14:01:32.9904 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a; Ip=[66.35.236.236]; Helo=[sj-itexedge04.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB0608 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The ciu_clk(Card Interface Unit Clock) on the SoCFPGA platform has a fixed divider of 4. Add the fixed clock divide code in the platform's clock setup code. Technically, this code could be be moved to dw_mmc-socfpga, like the Rockchip and Exynos, but I don't think it's necessary for a small change that is needed for the entire SoCFPGA family of SoCs. Also, "altr,dw-mshc-ciu-div" can be introduced to respresent the ciu divider, but since this divider is common across all SoCFPGA, I don't think its necessary. Signed-off-by: Dinh Nguyen CC: Seungwon Jeon CC: Jaehoon Chung CC: Chris Ball CC: Ulf Hansson CC: Doug Anderson --- drivers/mmc/host/dw_mmc-pltfm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index ec6dbcd..c92f790 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -26,13 +26,22 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_CIU_CLK_DIV 4 + static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *cmdr) { *cmdr |= SDMMC_CMD_USE_HOLD_REG; } +static int dw_mci_socfpga_setup_clock(struct dw_mci *host) +{ + host->bus_hz /= SOCFPGA_CIU_CLK_DIV; + return 0; +} + static const struct dw_mci_drv_data socfpga_drv_data = { .prepare_command = dw_mci_pltfm_prepare_command, + .setup_clock = dw_mci_socfpga_setup_clock, }; static const struct dw_mci_drv_data pistachio_drv_data = {