From patchwork Fri Sep 4 15:32:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 7124111 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1EDB6BEEC1 for ; Fri, 4 Sep 2015 15:36:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3D06820837 for ; Fri, 4 Sep 2015 15:36:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C64720836 for ; Fri, 4 Sep 2015 15:36:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759997AbbIDPet (ORCPT ); Fri, 4 Sep 2015 11:34:49 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:36393 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759992AbbIDPer (ORCPT ); Fri, 4 Sep 2015 11:34:47 -0400 Received: by pacwi10 with SMTP id wi10so27512333pac.3 for ; Fri, 04 Sep 2015 08:34:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1bUQwmGDXzzv3Fyr/7aOc/X+vN0thN9ySH8VpyQRkGE=; b=aRZtcQDY85wlF94F556fakSpnyCVqKgvkqs0hvLMSAWUsgIwED07lUIgQCiWMyX5eZ NRPkL0iI5KddIjWHl77FQ9B5szRS5A6fAOlsUlbGqIXfK6LUaK4e4Nd0BRYPGH6PSKK/ nYK6Hl2tip6xhNpgfx07MXcRpd+1XQbbxRXU6MS8IJHTSXvvUJdLQ5+gIZRfw7Ft59R3 SFavp0YJzKIEcw5TRoOwyJRv3gKiz+ttC/fCW6fz5CywG3MRHotkr3ieVJq254sZNwKE EtwzgnYeF4WkCsKrwuNZOPEsiZZ0ElKVME59KZPL4uqIUIQDKK7K59S9rY5Gs0UB3Idw jSEg== X-Gm-Message-State: ALoCoQldH6hYPRB1ptpZmEOzvR+aOAfd9ShzighViBJAlYUL36yb5WwfQeHHyfDgiHaCFDezQbO5 X-Received: by 10.66.221.68 with SMTP id qc4mr9382710pac.26.1441380887029; Fri, 04 Sep 2015 08:34:47 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.137]) by smtp.gmail.com with ESMTPSA id gs2sm2920151pbc.15.2015.09.04.08.34.43 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Sep 2015 08:34:45 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kliu5@marvell.com, ulf.hansson@linaro.org, Vaibhav Hiremath Subject: [PATCH 1/5] mmc: sdhci-pxav3: Enable pxa1928 device support Date: Fri, 4 Sep 2015 21:02:17 +0530 Message-Id: <1441380741-13115-2-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDHCI controller present in PXA1928 has few differences as far as register map is concerned. For example, PXAxxx PXA1928 ====== ======= SDCLK_DELAY field 0x10A 0x114 SDCLK_DELAY mask 0x1F 0x3FF SDCLK_DELAY shift 9 8 SDCLK_SEL shift 8 2 (SEL1) So in order to support multi-platform, use sdhci_pxa_regdata structure as a variant data according to platform. Note that, there are some more differences, which would be added as and when respective feature gets added to the driver. Signed-off-by: Vaibhav Hiremath --- drivers/mmc/host/sdhci-pxav3.c | 62 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 6d4bad4..aecae04 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -42,9 +42,6 @@ #define PXAV3_RPM_DELAY_MS 50 #define SD_CLOCK_BURST_SIZE_SETUP 0x10A -#define SDCLK_SEL 0x100 -#define SDCLK_DELAY_SHIFT 9 -#define SDCLK_DELAY_MASK 0x1f #define SD_CFG_FIFO_PARAM 0x100 #define SDCFG_GEN_PAD_CLK_ON BIT(6) @@ -58,11 +55,25 @@ #define SDCE_MISC_INT BIT(2) #define SDCE_MISC_INT_EN BIT(1) +#define SD_RX_CFG_REG 0x114 + /* IO Power control */ #define IO_PWR_AKEY_ASFAR 0xbaba #define IO_PWR_AKEY_ASSAR 0xeb10 #define IO_PWR_MMC1_PAD_1V8 BIT(2) +struct sdhci_pxa_data { + u32 sdclk_delay_reg; + u32 sdclk_delay_mask; + u8 sdclk_delay_shift; + u8 sdclk_sel_mask; + u8 sdclk_sel_shift; + /* + * We have few more differences, add them along with their + * respective feature support + */ +}; + struct sdhci_pxa { struct clk *clk_core; struct clk *clk_io; @@ -70,6 +81,24 @@ struct sdhci_pxa { void __iomem *sdio3_conf_reg; void __iomem *io_pwr_reg; void __iomem *io_pwr_lock_reg; + struct sdhci_pxa_data *data; +}; + +static struct sdhci_pxa_data pxav3_data_v1 = { + .sdclk_delay_reg = SD_CLOCK_BURST_SIZE_SETUP, + .sdclk_delay_mask = 0x1F, + .sdclk_delay_shift = 9, + .sdclk_sel_mask = 0x1, + .sdclk_sel_shift = 8, +}; + +static struct sdhci_pxa_data pxav3_data_v2 = { + .sdclk_delay_reg = SD_RX_CFG_REG, + .sdclk_delay_mask = 0x3FF, + .sdclk_delay_shift = 8, + /* Only set SDCLK_SEL1, as driver uses default value of SDCLK_SEL0 */ + .sdclk_sel_mask = 0x3, + .sdclk_sel_shift = 2, /* SDCLK_SEL1 */ }; /* @@ -183,6 +212,8 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask) { struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; sdhci_reset(host, mask); @@ -193,12 +224,14 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask) */ if (pdata && 0 != pdata->clk_delay_cycles) { u16 tmp; - - tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); - tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) - << SDCLK_DELAY_SHIFT; - tmp |= SDCLK_SEL; - writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); + struct sdhci_pxa_data *data = pxa->data; + + tmp = readw(host->ioaddr + data->sdclk_delay_reg); + tmp |= (pdata->clk_delay_cycles & data->sdclk_delay_mask) + << data->sdclk_delay_shift; + tmp &= ~(data->sdclk_sel_mask << data->sdclk_sel_shift); + tmp |= 1 << data->sdclk_sel_shift; + writew(tmp, host->ioaddr + data->sdclk_delay_reg); } } } @@ -363,10 +396,16 @@ static struct sdhci_pltfm_data sdhci_pxav3_pdata = { #ifdef CONFIG_OF static const struct of_device_id sdhci_pxav3_of_match[] = { { - .compatible = "mrvl,pxav3-mmc", + .compatible = "mrvl,pxav3-mmc", + .data = (void *)&pxav3_data_v1, + }, + { + .compatible = "marvell,armada-380-sdhci", + .data = (void *)&pxav3_data_v1, }, { - .compatible = "marvell,armada-380-sdhci", + .compatible = "marvell,pxav3-1928-sdhci", + .data = (void *)&pxav3_data_v2, }, {}, }; @@ -470,6 +509,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) goto err_of_parse; sdhci_get_of_property(pdev); pdata = pxav3_get_mmc_pdata(dev); + pxa->data = (struct sdhci_pxa_data *)match->data; pdev->dev.platform_data = pdata; } else if (pdata) { /* on-chip device */