From patchwork Wed Oct 21 10:49:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaehoon Chung X-Patchwork-Id: 7456121 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B22739F4DD for ; Wed, 21 Oct 2015 10:49:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D4C4220822 for ; Wed, 21 Oct 2015 10:49:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 57C16207ED for ; Wed, 21 Oct 2015 10:49:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752215AbbJUKtr (ORCPT ); Wed, 21 Oct 2015 06:49:47 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:41319 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752382AbbJUKtq (ORCPT ); Wed, 21 Oct 2015 06:49:46 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NWK0027RGQW3JC0@mailout3.samsung.com> for linux-mmc@vger.kernel.org; Wed, 21 Oct 2015 19:49:44 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.112]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id C8.66.05342.7CD67265; Wed, 21 Oct 2015 19:49:44 +0900 (KST) X-AuditID: cbfee690-f794e6d0000014de-82-56276dc7419a Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 5F.61.23663.7CD67265; Wed, 21 Oct 2015 19:49:43 +0900 (KST) Received: from localhost.localdomain ([10.252.81.186]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NWK00MJ3GQVZJ90@mmp2.samsung.com>; Wed, 21 Oct 2015 19:49:43 +0900 (KST) From: Jaehoon Chung To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, k.kozlowski@samsung.com, linux.amoon@gmail.com, jh80.chung@gmail.com, Jaehoon Chung Subject: [PATCH 2/2] mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode Date: Wed, 21 Oct 2015 19:49:42 +0900 Message-id: <1445424582-7940-2-git-send-email-jh80.chung@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1445424582-7940-1-git-send-email-jh80.chung@samsung.com> References: <1445424582-7940-1-git-send-email-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsWyRsSkQPdErnqYQcdsJouLV5YyW9z41cZq 8fqFocWR//2MFus23mK3OL423IHNY+esu+wed67tYfPo27KK0ePzJrkAligum5TUnMyy1CJ9 uwSujL0LZrIXHGCr2HbiDmsD4zLWLkZODgkBE4ltf48wQdhiEhfurWfrYuTiEBJYwShx5tRe Zpii/qvv2SESsxgltq54COX8YJS41PeSEaSKTUBHYvu342CjRARkJX7+uQA2ilmgi1Gi5cMc sCJhAS+JN5tegRWxCKhKrDq+jwXE5hVwlVjz5AkjxDo5iZPHJgPdx8HBKeAmsapHDSQsBFSy 4NtZFpCZEgL97BLrJ+xkhZgjIPFt8iEWkHoJoMWbDkBdLSlxcMUNlgmMwgsYGVYxiqYWJBcU J6UXmegVJ+YWl+al6yXn525iBAb06X/PJuxgvHfA+hCjAAejEg/vh4VqYUKsiWXFlbmHGE2B NkxklhJNzgfGTV5JvKGxmZGFqYmpsZG5pZmSOO9rqZ/BQgLpiSWp2ampBalF8UWlOanFhxiZ ODilGhiX7+1ZJ6J8q3JKY57fN3aZyAYL7tZeg+KP9W+FrJdNXxG+xeaYTHco5/Q1CeuSpize tWPHj2uHdHODFMwjn949U9Czxr2/8tWpZ163Q/tEgy4IxhkIWs99xqMeLve7uGvt26AITteY z4ZstoYbH0oyrfaW+nPHj+HIRKvoNV5PLmzYIXnjbY4SS3FGoqEWc1FxIgBmu/fsYwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLIsWRmVeSWpSXmKPExsVy+t9jQd3juephBvdnWltcvLKU2eLGrzZW i9cvDC2O/O9ntFi38Ra7xfG14Q5sHjtn3WX3uHNtD5tH35ZVjB6fN8kFsEQ1MNpkpCampBYp pOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAO1WUihLzCkFCgUkFhcr 6dthmhAa4qZrAdMYoesbEgTXY2SABhLWMGbsXTCTveAAW8W2E3dYGxiXsXYxcnJICJhI9F99 zw5hi0lcuLeerYuRi0NIYBajxNYVD9khnB+MEpf6XjKCVLEJ6Ehs/3acCcQWEZCV+PnnAlgH s0AXo0TLhzlgRcICXhJvNr0CK2IRUJVYdXwfC4jNK+AqsebJE0aIdXISJ49NBjqDg4NTwE1i VY8aSFgIqGTBt7MsExh5FzAyrGKUSC1ILihOSs81zEst1ytOzC0uzUvXS87P3cQIjppnUjsY D+5yP8QowMGoxMP7YaFamBBrYllxZe4hRgkOZiUR3imJ6mFCvCmJlVWpRfnxRaU5qcWHGE2B 7prILCWanA+M6LySeENjEzMjSyNzQwsjY3Mlcd4bhxjChATSE0tSs1NTC1KLYPqYODilGhjX Fjntkn57cmug2tvJ1/jYY7U4l8X5zd5WqM6jWH7py25VHW4T8YXqXQrOrkbfLAu4TWaHiIkU lH3bek3+/daD8xjPn1+xssCwqGZJjvjSxZ2ybectjNbYa02UCkzaqDrl/YR1jjPTNgrUuv1l tG14NdX2uBSD4NdcxT+C1rNm3Vb4+mDax99KLMUZiYZazEXFiQD4yWZ2sAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When card is running with DDR mode, dwmmc needs to set DDR_REG bit at UHS_REG register. Before this patch, dwmmc controller doesn't consider this. If this patch is not applied, CRC or other error shoulds be occurred. Signed-off-by: Jaehoon Chung Reviewed-by: Alim Akhtar --- drivers/mmc/host/dw_mmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 6e600e8..cb31e8e 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1295,6 +1295,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) /* DDR mode set */ if (ios->timing == MMC_TIMING_MMC_DDR52 || + ios->timing == MMC_TIMING_UHS_DDR50 || ios->timing == MMC_TIMING_MMC_HS400) regs |= ((0x1 << slot->id) << 16); else