From patchwork Tue Dec 22 18:41:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 7906531 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 321399F3CD for ; Tue, 22 Dec 2015 18:41:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 55B1C204D2 for ; Tue, 22 Dec 2015 18:41:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 59092204DE for ; Tue, 22 Dec 2015 18:41:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754557AbbLVSlT (ORCPT ); Tue, 22 Dec 2015 13:41:19 -0500 Received: from ns.lynxeye.de ([87.118.118.114]:44234 "EHLO lynxeye.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754610AbbLVSlR (ORCPT ); Tue, 22 Dec 2015 13:41:17 -0500 Received: by lynxeye.de (Postfix, from userid 501) id C089926C2009; Tue, 22 Dec 2015 19:41:15 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from tellur.intern.lynxeye.de (p57B5F3A9.dip0.t-ipconnect.de [87.181.243.169]) by lynxeye.de (Postfix) with ESMTPA id E713426C2002; Tue, 22 Dec 2015 19:41:11 +0100 (CET) From: Lucas Stach To: Ulf Hansson Cc: Stephen Warren , Thierry Reding , Alexandre Courbot , linux-mmc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 4/5] mmc: tegra: enable UHS-I modes Date: Tue, 22 Dec 2015 19:41:03 +0100 Message-Id: <1450809664-11360-5-git-send-email-dev@lynxeye.de> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1450809664-11360-1-git-send-email-dev@lynxeye.de> References: <1450809664-11360-1-git-send-email-dev@lynxeye.de> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Keep the quirk bits, as Tegra30 and Tegra114 host have different levels of support for UHS-I modes and so need different spare bits to be set, but change the logic to be positive. Signed-off-by: Lucas Stach --- drivers/mmc/host/sdhci-tegra.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 0201549..20084f8 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -45,9 +45,9 @@ #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) -#define NVQUIRK_DISABLE_SDR50 BIT(3) -#define NVQUIRK_DISABLE_SDR104 BIT(4) -#define NVQUIRK_DISABLE_DDR50 BIT(5) +#define NVQUIRK_ENABLE_SDR50 BIT(3) +#define NVQUIRK_ENABLE_SDR104 BIT(4) +#define NVQUIRK_ENABLE_DDR50 BIT(5) struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; @@ -144,18 +144,18 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) /* Erratum: Enable SDHCI spec v3.00 support */ if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; - /* Don't advertise UHS modes which aren't supported yet */ - if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) - misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; - if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) - misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; - if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) - misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; + /* Advertise UHS modes as supported by host */ + if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) + misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; + if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) + misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; + if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) + misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; - if (!(soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)) + if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); @@ -305,8 +305,8 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { static const struct sdhci_tegra_soc_data soc_data_tegra30 = { .pdata = &sdhci_tegra30_pdata, .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | - NVQUIRK_DISABLE_SDR50 | - NVQUIRK_DISABLE_SDR104, + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104, }; static const struct sdhci_ops tegra114_sdhci_ops = { @@ -335,9 +335,9 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { static const struct sdhci_tegra_soc_data soc_data_tegra114 = { .pdata = &sdhci_tegra114_pdata, - .nvquirks = NVQUIRK_DISABLE_SDR50 | - NVQUIRK_DISABLE_DDR50 | - NVQUIRK_DISABLE_SDR104, + .nvquirks = NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_DDR50 | + NVQUIRK_ENABLE_SDR104, }; static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { @@ -353,9 +353,9 @@ static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { static const struct sdhci_tegra_soc_data soc_data_tegra210 = { .pdata = &sdhci_tegra210_pdata, - .nvquirks = NVQUIRK_DISABLE_SDR50 | - NVQUIRK_DISABLE_DDR50 | - NVQUIRK_DISABLE_SDR104, + .nvquirks = NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_DDR50 | + NVQUIRK_ENABLE_SDR104, }; static const struct of_device_id sdhci_tegra_dt_match[] = { @@ -402,7 +402,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_parse_dt; - if (!(tegra_host->soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)) + if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) host->mmc->caps |= MMC_CAP_1_8V_DDR; tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",