From patchwork Thu Jan 21 02:01:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaehoon Chung X-Patchwork-Id: 8076651 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 415C2BEEE5 for ; Thu, 21 Jan 2016 02:01:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2CBF9205EA for ; Thu, 21 Jan 2016 02:01:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB53F205DA for ; Thu, 21 Jan 2016 02:01:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752029AbcAUCBX (ORCPT ); Wed, 20 Jan 2016 21:01:23 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:49791 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751825AbcAUCBX (ORCPT ); Wed, 20 Jan 2016 21:01:23 -0500 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O1A02WCN5M1XR10@mailout1.samsung.com> for linux-mmc@vger.kernel.org; Thu, 21 Jan 2016 11:01:13 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.113]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 09.CF.04949.9EB30A65; Thu, 21 Jan 2016 11:01:13 +0900 (KST) X-AuditID: cbfee68d-f79646d000001355-d0-56a03be98d27 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 00.74.13906.9EB30A65; Thu, 21 Jan 2016 11:01:13 +0900 (KST) Received: from localhost.localdomain ([10.113.62.216]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O1A00KZC5LWWH20@mmp1.samsung.com>; Thu, 21 Jan 2016 11:01:13 +0900 (KST) From: Jaehoon Chung To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, shawn.lin@rock-chips.com, Jaehoon Chung Subject: [PATCH] mmc: dw_mmc: remove the prepare_command hook Date: Thu, 21 Jan 2016 11:01:06 +0900 Message-id: <1453341666-26703-1-git-send-email-jh80.chung@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPLMWRmVeSWpSXmKPExsWyRsSkUPel9YIwg2W/NS1u/GpjtTjyv5/R 4s6T9awWx9eGO7B43Lm2h83j76z9LB59W1YxenzeJBfAEsVlk5Kak1mWWqRvl8CVceL4ZbaC JVYV+3+cYG9gvGjQxcjJISFgIrH21DYmCFtM4sK99WxdjFwcQgIrGCXav99lhCk6OWklC0Ri KaPE90v/mCCcH4wSD6/PBqtiE9CR2P7tONgoEQFZiZ9/LrCB2MwCcRKLjv5kB7GFBWwlvuy5 DFbPIqAqMWXxImYQm1fATeLKxJnsENvkJE4em8wKskBC4DWbxKHVS1khGgQkvk0+BHQGB1BC VmLTAWaIekmJgytusExgFFzAyLCKUTS1ILmgOCm9yFCvODG3uDQvXS85P3cTIzAcT/971ruD 8fYB60OMAhyMSjy8N67NDxNiTSwrrsw9xGgKtGEis5Rocj4w6PNK4g2NzYwsTE1MjY3MLc2U xHkVpX4GCwmkJ5akZqemFqQWxReV5qQWH2Jk4uCUamA8tjdz3r///Od2VPzbdsqii6nE9Ite l/vqP/+nBiyUeVVY/1lJZLmbztOTB/RWrciMTpBXieYPDjv1oe3vzjs6V5m3ZWfcPVZ4U2C3 8cFNsVa/hSU2tn2RWft1X3aI3ZY3wQ93rfx8cmV1zU396v1mCuIGl1XZs44yHjoQrzNPz/nW StV5BWb3lFiKMxINtZiLihMBPjYeb0ICAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRmVeSWpSXmKPExsVy+t9jAd2X1gvCDCZvUrG48auN1eLI/35G iztP1rNaHF8b7sDicefaHjaPv7P2s3j0bVnF6PF5k1wAS1QDo01GamJKapFCal5yfkpmXrqt kndwvHO8qZmBoa6hpYW5kkJeYm6qrZKLT4CuW2YO0EolhbLEnFKgUEBicbGSvh2mCaEhbroW MI0Rur4hQXA9RgZoIGENY8aJ45fZCpZYVez/cYK9gfGiQRcjJ4eEgInEyUkrWSBsMYkL99az dTFycQgJLGWU+H7pHxOE84NR4uH12YwgVWwCOhLbvx1nArFFBGQlfv65wAZiMwvESSw6+pMd xBYWsJX4sucyWD2LgKrElMWLmEFsXgE3iSsTZ7JDbJOTOHlsMusERu4FjAyrGCVSC5ILipPS cw3zUsv1ihNzi0vz0vWS83M3MYJD/pnUDsaDu9wPMQpwMCrx8BrcnB8mxJpYVlyZe4hRgoNZ SYRXTmVBmBBvSmJlVWpRfnxRaU5q8SFGU6ADJjJLiSbnA+MxryTe0NjEzMjSyNzQwsjYXEmc t/ZSZJiQQHpiSWp2ampBahFMHxMHp1QDo+P7Y0t+TGV+/41VJSz2Lcuus9+O/S+v2f67IbH5 rmTd55cP3Lf7XDRa/EYnfPKc2w9v2KXX8wqmrDHbHbgqYls+14oE//ZX25TfCVXosfCy6s74 6BD+8938Ar5OvYwNQg/frTN4wcc54Yn229shLyVd03efOvystv6KpOm6pywz/a/2OCUEdCqx FGckGmoxFxUnAgA8OsIUjwIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch removes the prepare_command hook from entire dw_mmc driver. Now, almost all SoCs are using by default, except Exynos. It seems that dwmmc controller is using unnecessary hook. To know whether needs to set this bit or not, add the DW_MMC_CARD_NO_USE_HOLD bit. If some SoCs need to disable this in future, just set the DW_MMC_CARD_NO_USE_HOLD bit. set_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags), Signed-off-by: Jaehoon Chung Tested-by: Shawn Lin Reviewed-by: Shawn Lin --- drivers/mmc/host/dw_mmc-exynos.c | 31 ++++++++++--------------------- drivers/mmc/host/dw_mmc-pltfm.c | 19 ++----------------- drivers/mmc/host/dw_mmc-rockchip.c | 7 ------- drivers/mmc/host/dw_mmc.c | 5 ++--- drivers/mmc/host/dw_mmc.h | 3 +-- 5 files changed, 15 insertions(+), 50 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 3a7e835..8790f2a 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -145,6 +145,16 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); + + /* + * Exynos4412 and Exynos5250 extends the use of CMD register with the + * use of bit 29 (which is reserved on standard MSHC controllers) for + * optionally bypassing the HOLD register for command and data. The + * HOLD register should be bypassed in case there is no phase shift + * applied on CMD/DATA that is sent to the card. + */ + if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel)) + set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags); } #ifdef CONFIG_PM_SLEEP @@ -202,26 +212,6 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) #define dw_mci_exynos_resume_noirq NULL #endif /* CONFIG_PM_SLEEP */ -static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr) -{ - struct dw_mci_exynos_priv_data *priv = host->priv; - /* - * Exynos4412 and Exynos5250 extends the use of CMD register with the - * use of bit 29 (which is reserved on standard MSHC controllers) for - * optionally bypassing the HOLD register for command and data. The - * HOLD register should be bypassed in case there is no phase shift - * applied on CMD/DATA that is sent to the card. - */ - if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { - if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64))) - *cmdr |= SDMMC_CMD_USE_HOLD_REG; - } else { - if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL))) - *cmdr |= SDMMC_CMD_USE_HOLD_REG; - } -} - static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) { struct dw_mci_exynos_priv_data *priv = host->priv; @@ -500,7 +490,6 @@ static const struct dw_mci_drv_data exynos_drv_data = { .caps = exynos_dwmmc_caps, .init = dw_mci_exynos_priv_init, .setup_clock = dw_mci_exynos_setup_clock, - .prepare_command = dw_mci_exynos_prepare_command, .set_ios = dw_mci_exynos_set_ios, .parse_dt = dw_mci_exynos_parse_dt, .execute_tuning = dw_mci_exynos_execute_tuning, diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 81bdeeb..c0bb0c7 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -26,19 +26,6 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" -static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *cmdr) -{ - *cmdr |= SDMMC_CMD_USE_HOLD_REG; -} - -static const struct dw_mci_drv_data socfpga_drv_data = { - .prepare_command = dw_mci_pltfm_prepare_command, -}; - -static const struct dw_mci_drv_data pistachio_drv_data = { - .prepare_command = dw_mci_pltfm_prepare_command, -}; - int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -94,10 +81,8 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", - .data = &socfpga_drv_data }, - { .compatible = "img,pistachio-dw-mshc", - .data = &pistachio_drv_data }, + { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "img,pistachio-dw-mshc", }, {}, }; MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match); diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index d9c92f3..84e50f3 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -26,11 +26,6 @@ struct dw_mci_rockchip_priv_data { int default_sample_phase; }; -static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr) -{ - *cmdr |= SDMMC_CMD_USE_HOLD_REG; -} - static int dw_mci_rk3288_setup_clock(struct dw_mci *host) { host->bus_hz /= RK3288_CLKGEN_DIV; @@ -240,12 +235,10 @@ static int dw_mci_rockchip_init(struct dw_mci *host) } static const struct dw_mci_drv_data rk2928_drv_data = { - .prepare_command = dw_mci_rockchip_prepare_command, .init = dw_mci_rockchip_init, }; static const struct dw_mci_drv_data rk3288_drv_data = { - .prepare_command = dw_mci_rockchip_prepare_command, .set_ios = dw_mci_rk3288_set_ios, .execute_tuning = dw_mci_rk3288_execute_tuning, .parse_dt = dw_mci_rk3288_parse_dt, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index ffef24a..7238f66 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -234,7 +234,6 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) struct mmc_data *data; struct dw_mci_slot *slot = mmc_priv(mmc); struct dw_mci *host = slot->host; - const struct dw_mci_drv_data *drv_data = slot->host->drv_data; u32 cmdr; cmd->error = -EINPROGRESS; @@ -296,8 +295,8 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) cmdr |= SDMMC_CMD_DAT_WR; } - if (drv_data && drv_data->prepare_command) - drv_data->prepare_command(slot->host, &cmdr); + if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) + cmdr |= SDMMC_CMD_USE_HOLD_REG; return cmdr; } diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index a14b7fc..68d5da2 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -268,6 +268,7 @@ struct dw_mci_slot { #define DW_MMC_CARD_PRESENT 0 #define DW_MMC_CARD_NEED_INIT 1 #define DW_MMC_CARD_NO_LOW_PWR 2 +#define DW_MMC_CARD_NO_USE_HOLD 3 int id; int sdio_id; }; @@ -277,7 +278,6 @@ struct dw_mci_slot { * @caps: mmc subsystem specified capabilities of the controller(s). * @init: early implementation specific initialization. * @setup_clock: implementation specific clock configuration. - * @prepare_command: handle CMD register extensions. * @set_ios: handle bus specific extensions. * @parse_dt: parse implementation specific device tree properties. * @execute_tuning: implementation specific tuning procedure. @@ -290,7 +290,6 @@ struct dw_mci_drv_data { unsigned long *caps; int (*init)(struct dw_mci *host); int (*setup_clock)(struct dw_mci *host); - void (*prepare_command)(struct dw_mci *host, u32 *cmdr); void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); int (*parse_dt)(struct dw_mci *host); int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);