From patchwork Fri Feb 19 20:16:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 8363681 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8C331C0553 for ; Fri, 19 Feb 2016 20:17:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8817B2047B for ; Fri, 19 Feb 2016 20:17:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7DBE22047D for ; Fri, 19 Feb 2016 20:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2992533AbcBSURN (ORCPT ); Fri, 19 Feb 2016 15:17:13 -0500 Received: from sauhun.de ([89.238.76.85]:40786 "EHLO pokefinder.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1949378AbcBSURM (ORCPT ); Fri, 19 Feb 2016 15:17:12 -0500 Received: from p4fe2573c.dip0.t-ipconnect.de ([79.226.87.60]:49128 helo=localhost) by pokefinder.org with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1aWrUE-0007hk-Be; Fri, 19 Feb 2016 21:17:10 +0100 From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Ben Hutchings , Dirk Behme , Wolfram Sang , Ulrich Hecht Subject: [RFC 1/7] pinctrl: sh-pfc: r8a7790: Implement voltage switching for SDHI Date: Fri, 19 Feb 2016 21:16:37 +0100 Message-Id: <1455913003-6140-2-git-send-email-wsa@the-dreams.de> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1455913003-6140-1-git-send-email-wsa@the-dreams.de> References: <1455913003-6140-1-git-send-email-wsa@the-dreams.de> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Wolfram Sang All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Implement the {get,set}_io_voltage operations and set the related capability flag for the associated pins. Signed-off-by: Ben Hutchings Signed-off-by: Wolfram Sang Cc: Ulrich Hecht --- The get/set-functions introduced here are the same for all Gen2, except for the pin-sanity checks at the beginning. Somehow a generic function might be nice for consistency reasons (I don't care so much about the code savings). But not sure if it is worth the hazzle. @Uli, Geert: Since bias support is probably similar, what do you think? Does it make sense to add gen{2,3}.c? drivers/pinctrl/sh-pfc/core.c | 2 +- drivers/pinctrl/sh-pfc/core.h | 1 + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 60 +++++++++++++++++++++++++++++++++++- 3 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 181ea98a63b7ab..315f9db9f5affe 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -88,7 +88,7 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc, return 0; } -static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) +void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) { struct sh_pfc_window *window; phys_addr_t address = reg; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 62f53b22ae8500..ca041a753a2521 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -59,6 +59,7 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc); int sh_pfc_register_pinctrl(struct sh_pfc *pfc); int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); +void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 address); u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width); void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, u32 data); diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 0f4d48f9400ba0..ed51d67609050d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -21,16 +21,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include "core.h" #include "sh_pfc.h" +/* + * All pins assigned to GPIO bank 3 can be used for SD interfaces in + * which case they support both 3.3V and 1.8V signalling. + */ #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_30(1, fn, sfx), \ PORT_GP_30(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx) @@ -4691,6 +4696,53 @@ static const char * const vin3_groups[] = { "vin3_clk", }; +#define IOCTRL6 0xe606008c + +static int r8a7790_get_io_voltage(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *reg; + u32 data, mask; + + if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin)) + return -EINVAL; + + reg = sh_pfc_phys_to_virt(pfc, IOCTRL6); + data = ioread32(reg); + + /* Bits in IOCTRL6 are numbered in opposite order to pins */ + mask = 0x80000000 >> (pin & 0x1f); + + return (data & mask) ? 3300 : 1800; +} + +static int r8a7790_set_io_voltage(struct sh_pfc *pfc, unsigned int pin, u16 mV) +{ + void __iomem *reg; + u32 data, mask; + + if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin)) + return -EINVAL; + + if (mV != 1800 && mV != 3300) + return -EINVAL; + + reg = sh_pfc_phys_to_virt(pfc, IOCTRL6); + data = ioread32(reg); + + /* Bits in IOCTRL6 are numbered in opposite order to pins */ + mask = 0x80000000 >> (pin & 0x1f); + + if (mV == 3300) + data |= mask; + else + data &= ~mask; + + iowrite32(~data, sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg)); + iowrite32(data, reg); + + return 0; +} + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), @@ -5690,8 +5742,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static const struct sh_pfc_soc_operations pinmux_ops = { + .get_io_voltage = r8a7790_get_io_voltage, + .set_io_voltage = r8a7790_set_io_voltage, +}; + const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", + .ops = &pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },