From patchwork Tue Jun 7 22:44:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9162747 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F07DA60832 for ; Tue, 7 Jun 2016 22:47:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E2B9928360 for ; Tue, 7 Jun 2016 22:47:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D77832836E; Tue, 7 Jun 2016 22:47:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7BDB928360 for ; Tue, 7 Jun 2016 22:47:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423507AbcFGWpR (ORCPT ); Tue, 7 Jun 2016 18:45:17 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:33494 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423500AbcFGWpP (ORCPT ); Tue, 7 Jun 2016 18:45:15 -0400 Received: by mail-pf0-f175.google.com with SMTP id y124so22387815pfy.0 for ; Tue, 07 Jun 2016 15:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bb/ZoNbDtV8sgWPwryyr8kmpIEkov0imvHwjmvnj8Tc=; b=ib1i8emW8Q1HXPglIhsMXBSIugsUhvgkGWqgwEp7I4XokY3cY7cGTknz9IDzeFk7LW 2yjj9ECzF3nHuABdZ15kmv+cv3aZEYhulXyVXVbRolbzaI5wayYnlX4JrwUuQ9OXe1JY yfPbNra4nP0TBIRVGS8T1iHT/2pK1D6qUVdPc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bb/ZoNbDtV8sgWPwryyr8kmpIEkov0imvHwjmvnj8Tc=; b=E8YerThGCHb1vsietVienbZblnifvsqpwdjyy56o8mpbH9xzPZ3ofps1texP+Rt9dc MBG8kB3fj/SxfvWFpViH43ESOtNCGNWj5+vw88Es4JgUlNmrwOJGix/nrwaM7XMt+T8V ZQF42Df+6IioYrL6m+c+6dhi8nh2KlLvFQkbP/1ZJJqhh90o3ey3cL+oM/sqzbQ4IEWk 0n5FofcqQ8/piJ8jI5uCSZr4Bt0qzMbnh89tYaY4D2v5nDsAmLD38KfJXkHj8AEYFiEL ijq11h/7fx7ziwuTLHpSRlDkG6dIyy4LMBJJWh0/5X5eSQfezniK7XKEt2rqR6qTgRu1 Jt5A== X-Gm-Message-State: ALyK8tLzn1OBtBlkbJ+zG721siew1/tgEmm29KguZO2I6kd/vfAo2d3n/F1C2adf3Lcb1xSf X-Received: by 10.98.89.207 with SMTP id k76mr1934899pfj.166.1465339514428; Tue, 07 Jun 2016 15:45:14 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id 4sm37641782pfm.15.2016.06.07.15.45.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Jun 2016 15:45:14 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Douglas Anderson , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Date: Tue, 7 Jun 2016 15:44:39 -0700 Message-Id: <1465339484-969-7-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465339484-969-1-git-send-email-dianders@chromium.org> References: <1465339484-969-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work with arasan,sdhci-5.1) need to know the card clock in order to function properly. Let's expose this clock using a standard device tree mechanism so that the PHY can get access to and query the card clock. Signed-off-by: Douglas Anderson Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index b67e623ca1ff..074d03e630ec 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -30,6 +30,12 @@ Optional Properties: - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) used to access core corecfg registers. Offsets of registers in this syscon are determined based on the main compatible string for the device. + - clock-output-names: If specified, this will be the name of the card clock + which will be exposed by this device. Required if #clock-cells is + specified. + - #clock-cells: If specified this should be the value <0>. With this property + in place we will export a clock representing the Card Clock. This clock + is expected to be consumed by our PHY. You must also specify Example: sdhci@e0100000 { @@ -61,7 +67,9 @@ Example: arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; + clock-output-names = "emmc_cardclock"; phys = <&emmc_phy>; phy-names = "phy_arasan"; + #clock-cells = <0>; status = "disabled"; };