From patchwork Tue Jun 7 22:44:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9162763 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CACF060467 for ; Tue, 7 Jun 2016 22:48:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCA2C28360 for ; Tue, 7 Jun 2016 22:48:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B17822836E; Tue, 7 Jun 2016 22:48:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2843F28360 for ; Tue, 7 Jun 2016 22:48:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161504AbcFGWrv (ORCPT ); Tue, 7 Jun 2016 18:47:51 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:33942 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423503AbcFGWpQ (ORCPT ); Tue, 7 Jun 2016 18:45:16 -0400 Received: by mail-pf0-f179.google.com with SMTP id 62so81984352pfd.1 for ; Tue, 07 Jun 2016 15:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TieetZc/Q9llODj0n5VPZ96Mrb5PS6gA/4r/0YuL4Yc=; b=iIvA2cFstGlnb2qx6MdUEueQLsnUaWOBGlVximza6U9fdTMI4MRaoNhk5BBbUth47r UWvqISFFBHe7MRTQuxUIj7By/5iDjHRVoI46JN3fgigzlyM7UTFIC16wwZSlFVv9Gh8e 1TaLBXRuosaM4COMhQJlWZ9qavq283JxseC4Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TieetZc/Q9llODj0n5VPZ96Mrb5PS6gA/4r/0YuL4Yc=; b=AcdbDjFBJu+FzRpKRyl6VcbH98DsdSyg/idToRDOAU2LjV8xexKiJ9yjwOoFwNT0xN CzOAxZZX+M6epO86nXdn+Sxp9mOqsqsDY5C6sIj2ZJX6XFvvXphbl4r5wZRdVux+SOIT VAHJsISVbx39npFzDPgycOyZifMH0xXgsegkFDMqrPBXggi8u69QoqC8q/7mf3+T25+R LPJ/XMQe6IAQPHf56AfJo2ueLtTssKQ5DCe1VtIvA5fbQWYdx1IMMcKsksR3sYIYBhoM 3WTk7zL8i0oTPdnbgktAx7Xslrg54ge61Oq7trvsr5F5oIUWe6dU8xum+4M3ispNSPVi OSHA== X-Gm-Message-State: ALyK8tKE+WsIJfXQETgUQZYkJ2/U6q+/Lx3josa87PDXqGFC3AYKJUWkn7TuWGOhfJ3zrtJl X-Received: by 10.98.51.197 with SMTP id z188mr1977497pfz.100.1465339515335; Tue, 07 Jun 2016 15:45:15 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id 4sm37641782pfm.15.2016.06.07.15.45.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Jun 2016 15:45:15 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Douglas Anderson , michal.simek@xilinx.com, soren.brinkmann@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Date: Tue, 7 Jun 2016 15:44:40 -0700 Message-Id: <1465339484-969-8-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465339484-969-1-git-send-email-dianders@chromium.org> References: <1465339484-969-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work with arasan,sdhci-5.1) need to know the card clock in order to function properly. Let's add the ability to expose this clock. Any PHY that needs to know the clock rate can add a reference and query the clock rate. At the moment we register a CLK_GET_RATE_NOCACHE clock that simply allows querying the clock. This allows us to be less intrusive with regards to the main SDHCI driver, which has complex logic for adjusting the SD clock. Right now we always fully power cycle the PHY when the clock changes and that gives the PHY a good chance to query our clock. Signed-off-by: Douglas Anderson --- drivers/mmc/host/sdhci-of-arasan.c | 125 ++++++++++++++++++++++++++++++++++++- 1 file changed, 122 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 859ea1b21215..25852e4fd1b6 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -19,6 +19,7 @@ * your option) any later version. */ +#include #include #include #include @@ -73,17 +74,24 @@ struct sdhci_arasan_soc_ctl_map { /** * struct sdhci_arasan_data + * @host: Pointer to the main SDHCI host structure. * @clk_ahb: Pointer to the AHB clock * @phy: Pointer to the generic phy * @phy_on: True if the PHY is turned on. + * @sdcardclk_hw: Struct for the clock we might provide to a PHY. + * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. * @soc_ctl_map: Map to get offsets into soc_ctl registers. */ struct sdhci_arasan_data { + struct sdhci_host *host; struct clk *clk_ahb; struct phy *phy; bool phy_on; + struct clk_hw sdcardclk_hw; + struct clk *sdcardclk; + struct regmap *soc_ctl_base; const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; }; @@ -307,6 +315,31 @@ static const struct of_device_id sdhci_arasan_of_match[] = { MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); /** + * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate + * + * Return the current actual rate of the SD card clock. This can be used + * to communicate with out PHY. + * + * @hw: Pointer to the hardware clock structure. + * @parent_rate The parent rate (should be rate of clk_xin). + * Returns the card clock rate. + */ +static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + +{ + struct sdhci_arasan_data *sdhci_arasan = + container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); + struct sdhci_host *host = sdhci_arasan->host; + + return host->mmc->actual_clock; +} + +static const struct clk_ops arasan_sdcardclk_ops = { + .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, +}; + +/** * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq * * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This @@ -345,6 +378,83 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); } +/** + * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use + * + * Some PHY devices need to know what the actual card clock is. In order for + * them to find out, we'll provide a clock through the common clock framework + * for them to query. + * + * Note: without seriously re-architecting SDHCI's clock code and testing on + * all platforms, there's no way to create a totally beautiful clock here + * with all clock ops implemented. Instead, we'll just create a clock that can + * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock + * framework that we're doing things behind its back. This should be sufficient + * to create nice clean device tree bindings and later (if needed) we can try + * re-architecting SDHCI if we see some benefit to it. + * + * @sdhci_arasan: Our private data structure. + * @clk_xin: Pointer to the functional clock + * @dev: Pointer to our struct device. + * Returns 0 on success and error value on error + */ +static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, + struct clk *clk_xin, + struct device *dev) +{ + struct device_node *np = dev->of_node; + struct clk_init_data sdcardclk_init; + const char *parent_clk_name; + int ret; + + /* Providing a clock to the PHY is optional; no error if missing */ + if (!of_find_property(np, "#clock-cells", NULL)) + return 0; + + ret = of_property_read_string_index(np, "clock-output-names", 0, + &sdcardclk_init.name); + if (ret) { + dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); + return ret; + } + + parent_clk_name = __clk_get_name(clk_xin); + sdcardclk_init.parent_names = &parent_clk_name; + sdcardclk_init.num_parents = 1; + sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; + sdcardclk_init.ops = &arasan_sdcardclk_ops; + + sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; + sdhci_arasan->sdcardclk = + devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); + sdhci_arasan->sdcardclk_hw.init = NULL; + + ret = of_clk_add_provider(np, of_clk_src_simple_get, + sdhci_arasan->sdcardclk); + if (ret) + dev_err(dev, "Failed to add clock provider\n"); + + return ret; +} + +/** + * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() + * + * Should be called any time we're exiting and sdhci_arasan_register_sdclk() + * returned success. + * + * @dev: Pointer to our struct device. + */ +static void sdhci_arasan_unregister_sdclk(struct device *dev) +{ + struct device_node *np = dev->of_node; + + if (!of_find_property(np, "#clock-cells", NULL)) + return; + + of_clk_del_provider(dev->of_node); +} + static int sdhci_arasan_probe(struct platform_device *pdev) { int ret; @@ -362,6 +472,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + sdhci_arasan->host = host; match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); sdhci_arasan->soc_ctl_map = match->data; @@ -411,10 +522,14 @@ static int sdhci_arasan_probe(struct platform_device *pdev) sdhci_arasan_update_baseclkfreq(host); + ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); + if (ret) + goto clk_disable_all; + ret = mmc_of_parse(host->mmc); if (ret) { dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret); - goto clk_disable_all; + goto unreg_clk; } sdhci_arasan->phy = ERR_PTR(-ENODEV); @@ -425,13 +540,13 @@ static int sdhci_arasan_probe(struct platform_device *pdev) if (IS_ERR(sdhci_arasan->phy)) { ret = PTR_ERR(sdhci_arasan->phy); dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); - goto clk_disable_all; + goto unreg_clk; } ret = phy_init(sdhci_arasan->phy); if (ret < 0) { dev_err(&pdev->dev, "phy_init err.\n"); - goto clk_disable_all; + goto unreg_clk; } host->mmc_host_ops.hs400_enhanced_strobe = @@ -447,6 +562,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev) err_add_host: if (!IS_ERR(sdhci_arasan->phy)) phy_exit(sdhci_arasan->phy); +unreg_clk: + sdhci_arasan_unregister_sdclk(&pdev->dev); clk_disable_all: clk_disable_unprepare(clk_xin); clk_dis_ahb: @@ -469,6 +586,8 @@ static int sdhci_arasan_remove(struct platform_device *pdev) phy_exit(sdhci_arasan->phy); } + sdhci_arasan_unregister_sdclk(&pdev->dev); + ret = sdhci_pltfm_unregister(pdev); clk_disable_unprepare(clk_ahb);