From patchwork Mon Jun 13 23:04:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9174701 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AFA8760573 for ; Mon, 13 Jun 2016 23:10:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A153426861 for ; Mon, 13 Jun 2016 23:10:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95CAF2723E; Mon, 13 Jun 2016 23:10:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2519C26861 for ; Mon, 13 Jun 2016 23:10:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423381AbcFMXKk (ORCPT ); Mon, 13 Jun 2016 19:10:40 -0400 Received: from mail-pf0-f177.google.com ([209.85.192.177]:32794 "EHLO mail-pf0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423241AbcFMXEv (ORCPT ); Mon, 13 Jun 2016 19:04:51 -0400 Received: by mail-pf0-f177.google.com with SMTP id y124so50575448pfy.0 for ; Mon, 13 Jun 2016 16:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uh1u1nN0jafeWqGJzw5bf9y1/XiLvCu9aizMUqC8QCI=; b=J7vtZ/AtifZQh9VtWF4trqjUp86+JPREhD8DiJuUcxVWkLwkJcAVtqJZNRsSREkTCm UARXpvnXF4Ts8flwZBlWvGcO2kvM72X70BBpop5ZMzcAL4IwkHLsCX/eQQFt9HNBRAY4 vMa3hmCX1MllIRnRzsUoHxXcjlOm+w9DK319w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uh1u1nN0jafeWqGJzw5bf9y1/XiLvCu9aizMUqC8QCI=; b=OMXSaBkFZj6sNwxFfOMs0VnGJQQGbE5gHqt2aLiqd3PRO4wSfuQa9GbF6W7921VZ4y oJZGlEM7QVccHhL8F5KUAfQG7H7P1OINNU0IpMuPj3Wfmr4pUDS3QN6mLguGuZUkAt7x mtFEArzG8UE9+O1Hk6tqYa01NxMJfrL4Vp348dvrhOtfN1j5O5ib27Gjrb6uIQZFbJaG KGtFIlGfJanA5FOdeBgnLewzt1dUrstic9W/N7XrXOQUqHWaMJ2hPUZgbJWNOW9TXJ2I fksMAm6yI0BmAIezj/jFdWvZZJhYzWvSt8TUJXj9BFUqQlmrZEZeMkfPCiXwyuhznzzL uArw== X-Gm-Message-State: ALyK8tJX/03AG8eEbMOncH0CF73ZnhF+YrWFQS9pOnv1yw+9SP3oRNZrvNIvaiH1WJvEZA3s X-Received: by 10.98.26.148 with SMTP id a142mr13928704pfa.46.1465859090822; Mon, 13 Jun 2016 16:04:50 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id pk18sm8906434pab.27.2016.06.13.16.04.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 13 Jun 2016 16:04:50 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Douglas Anderson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/11] phy: rockchip-emmc: Increase lock time allowance Date: Mon, 13 Jun 2016 16:04:25 -0700 Message-Id: <1465859076-4868-2-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465859076-4868-1-git-send-email-dianders@chromium.org> References: <1465859076-4868-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Previous PHY code waited a fixed amount of time for the DLL to lock at power on time. Unfortunately, the time for the DLL to lock is actually a bit more dynamic and can be longer if the card clock is slower. Instead of waiting a fixed 30 us, let's now dynamically wait until the lock bit gets set. We'll wait up to 10 ms which should be OK even if the card clock is at the super slow 100 kHz. On its own, this change makes the PHY power on code a little more robust. Before this change the PHY was relying on the eMMC code to make sure the PHY was only powered on when the card clock was set to at least 50 MHz before, though this reliance wasn't documented anywhere. This change will be even more useful in future changes where we actually need to be able to wait for a DLL lock at slower clock speeds. Signed-off-by: Douglas Anderson Reviewed-by: Shawn Lin Acked-by: Kishon Vijay Abraham I --- Changes in v2: - Indicate that 5.1 ms is calculated (Shawn). drivers/phy/phy-rockchip-emmc.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c index a69f53630e67..2d059c046978 100644 --- a/drivers/phy/phy-rockchip-emmc.c +++ b/drivers/phy/phy-rockchip-emmc.c @@ -85,6 +85,7 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, { unsigned int caldone; unsigned int dllrdy; + unsigned long timeout; /* * Keep phyctrl_pdb and phyctrl_endll low to allow @@ -137,15 +138,26 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, PHYCTRL_ENDLL_MASK, PHYCTRL_ENDLL_SHIFT)); /* - * After enable analog DLL circuits, we need an extra 10.2us - * for dll to be ready for work. But according to testing, we - * find some chips need more than 25us. + * After enabling analog DLL circuits docs say that we need 10.2 us if + * our source clock is at 50 MHz and that lock time scales linearly + * with clock speed. If we are powering on the PHY and the card clock + * is super slow (like 100 kHZ) this could take as long as 5.1 ms as + * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms + * Hopefully we won't be running at 100 kHz, but we should still make + * sure we wait long enough. */ - udelay(30); - regmap_read(rk_phy->reg_base, - rk_phy->reg_offset + GRF_EMMCPHY_STATUS, - &dllrdy); - dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; + timeout = jiffies + msecs_to_jiffies(10); + do { + udelay(1); + + regmap_read(rk_phy->reg_base, + rk_phy->reg_offset + GRF_EMMCPHY_STATUS, + &dllrdy); + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; + if (dllrdy == PHYCTRL_DLLRDY_DONE) + break; + } while (!time_after(jiffies, timeout)); + if (dllrdy != PHYCTRL_DLLRDY_DONE) { pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n"); return -ETIMEDOUT;