From patchwork Mon Jun 20 17:56:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9188455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7C4F9601C0 for ; Mon, 20 Jun 2016 18:26:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F7602780C for ; Mon, 20 Jun 2016 18:26:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 63A3C27C2C; Mon, 20 Jun 2016 18:26:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E6EAB2780C for ; Mon, 20 Jun 2016 18:26:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755568AbcFTS0o (ORCPT ); Mon, 20 Jun 2016 14:26:44 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:35570 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753417AbcFTS0k (ORCPT ); Mon, 20 Jun 2016 14:26:40 -0400 Received: by mail-pa0-f44.google.com with SMTP id hl6so53064879pac.2 for ; Mon, 20 Jun 2016 11:25:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kTkaDjGHjftwClQAFlcT4j3NVb1e6PN1+HM1HgQ1QdY=; b=FQ0+7nyl+IMTTaQgL8vJEdGKaSXLrO50J7Vtr/hvTpm/k4JgH1xcbgznpVpm5Y/Z3F YE67Fw+2Rcg5PcQZsJuIXWKOrcosFA4uuDp5YXkcfq6aZMoqnubEJi1XaAcXp/TMyBqW jGmDpUCZtAMUnlbYsXR4QaYofGE4ncXKYuiCw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kTkaDjGHjftwClQAFlcT4j3NVb1e6PN1+HM1HgQ1QdY=; b=IZl9ZavnRnly2W8+AVKoPQEXn4ervBw3I8GGuCZH8CNKZG9uzl9UU0k9cWmKkI1CeD /bTPj5aK/vKecVrVC++m9psuHf7bihziH04NFncExcFlRCid1YKJpjZeNsS6ImRlWIcu fMuaiQ3KILJ0hcxKdSMx4XQNg1QZpmNgrre/gDu2iWM6WT3da3um8SNH4R6RWDvRnAIL e77Q+Zs6wb/nSmxvOWk7/Vb96Cr6P2kg990ucIrppH2mMUMOlSg5yychwjRpMclurD0y LPTqqNuWcaJ0UBgd3ZxK07wqRSSHUqcFkBKMCNYXUHnTFrh1graSNg1FVsTM0rhLPaVU iaIg== X-Gm-Message-State: ALyK8tL0awEc8d/AZj6aa0yZgfTtCSXIwJL96YzuQp4GFOBKW/DX8+DnyUfzxU2T5ewFOYZK X-Received: by 10.66.182.194 with SMTP id eg2mr23284225pac.159.1466445640425; Mon, 20 Jun 2016 11:00:40 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id c189sm60250353pfg.19.2016.06.20.11.00.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Jun 2016 11:00:39 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, Heiko Stuebner Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, groeck@chromium.org, Douglas Anderson , michal.simek@xilinx.com, soren.brinkmann@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/15] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Date: Mon, 20 Jun 2016 10:56:45 -0700 Message-Id: <1466445414-11974-7-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org> References: <1466445414-11974-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In commit 802ac39a5566 ("mmc: sdhci-of-arasan: fix set_clock when a phy is supported") we added code to power the PHY off and on whenever the clock was changed but we avoided doing the power cycle code when the clock was low speed. Let's now do it always. Although there may be other reasons for power cycling the PHY when the clock changes, one of the main reasons is that we need to give the DLL a chance to re-lock with the new clock. One of the things that the DLL is for is tuning the Receive Clock in HS200 mode and STRB in HS400 mode. Thus it is clear that we should make sure we power cycle the PHY (and wait for the DLL to lock) when we know we'll be in one of these two speed modes. That's what the original code did, though it used the clock rate rather than the speed mode. However, even in speed modes other than HS200,/HS400 the DLL is used for something since it can be clearly observed that the PHY doesn't function properly if you leave the DLL off. Although it appears less important to power cycle the PHY and wait for the DLL to lock when not in HS200/HS400 modes (no bugs were reported), it still seems wise to let the locking always happen nevertheless. Note: as part of this, we make sure that we never try to turn the PHY on when the clock is off (when the clock rate is 0). The PHY cannot work when the clock is off since its DLL can't lock. This change requires ("phy: rockchip-emmc: Increase lock time allowance") and will cause problems if picked without that change. Signed-off-by: Douglas Anderson Reviewed-by: Shawn Lin Tested-by: Heiko Stuebner Acked-by: Adrian Hunter --- Changes in v3: - Add collected tags Changes in v2: None drivers/mmc/host/sdhci-of-arasan.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 533e2bcb10bc..3ff1711077c2 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -35,11 +35,13 @@ /** * struct sdhci_arasan_data * @clk_ahb: Pointer to the AHB clock - * @phy: Pointer to the generic phy + * @phy: Pointer to the generic phy + * @phy_on: True if the PHY is turned on. */ struct sdhci_arasan_data { struct clk *clk_ahb; struct phy *phy; + bool phy_on; }; static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) @@ -61,12 +63,10 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); - bool ctrl_phy = false; - if (clock > MMC_HIGH_52_MAX_DTR && (!IS_ERR(sdhci_arasan->phy))) - ctrl_phy = true; + if (sdhci_arasan->phy_on && !IS_ERR(sdhci_arasan->phy)) { + sdhci_arasan->phy_on = false; - if (ctrl_phy) { spin_unlock_irq(&host->lock); phy_power_off(sdhci_arasan->phy); spin_lock_irq(&host->lock); @@ -74,7 +74,9 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_set_clock(host, clock); - if (ctrl_phy) { + if (host->mmc->actual_clock && !IS_ERR(sdhci_arasan->phy)) { + sdhci_arasan->phy_on = true; + spin_unlock_irq(&host->lock); phy_power_on(sdhci_arasan->phy); spin_lock_irq(&host->lock); @@ -257,12 +259,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev) goto clk_disable_all; } - ret = phy_power_on(sdhci_arasan->phy); - if (ret < 0) { - dev_err(&pdev->dev, "phy_power_on err.\n"); - goto err_phy_power; - } - host->mmc_host_ops.hs400_enhanced_strobe = sdhci_arasan_hs400_enhanced_strobe; } @@ -275,9 +271,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev) err_add_host: if (!IS_ERR(sdhci_arasan->phy)) - phy_power_off(sdhci_arasan->phy); -err_phy_power: - if (!IS_ERR(sdhci_arasan->phy)) phy_exit(sdhci_arasan->phy); clk_disable_all: clk_disable_unprepare(clk_xin);