From patchwork Tue Jul 12 13:53:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9225337 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D45460572 for ; Tue, 12 Jul 2016 13:53:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D73527165 for ; Tue, 12 Jul 2016 13:53:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 404BD2793D; Tue, 12 Jul 2016 13:53:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A503827165 for ; Tue, 12 Jul 2016 13:53:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750922AbcGLNxo (ORCPT ); Tue, 12 Jul 2016 09:53:44 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9475 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750879AbcGLNxn (ORCPT ); Tue, 12 Jul 2016 09:53:43 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 12 Jul 2016 06:52:56 -0700 Received: from HQMAIL103.nvidia.com ([172.20.187.11]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 12 Jul 2016 06:51:46 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 12 Jul 2016 06:51:46 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 12 Jul 2016 13:53:42 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 12 Jul 2016 13:53:42 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 12 Jul 2016 13:53:41 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.110]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 12 Jul 2016 06:53:41 -0700 From: Jon Hunter To: Adrian Hunter , Ulf Hansson , Stephen Warren , "Thierry Reding" , Alexandre Courbot CC: , , , Jon Hunter Subject: [PATCH V2 1/2] mmc: sdhci: Request regulators before reading capabilities Date: Tue, 12 Jul 2016 14:53:36 +0100 Message-ID: <1468331617-22265-1-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The capabilities of the SDHCI host controller are read early during the SDHCI host initialisation in sdhci_setup_host() and before any regulators for the host have been requested. This means that if the host supports some high-speed modes (according to its capabilities register), but the board cannot because the appropriate voltage regulator is not available, then the host cannot easily override the capabilities that are supported. To allow a SDHCI host controller to determine if it can support high speed modes via the presense of the MMC regulators, request the regulators before reading the capabilites of the host controller. This will allow the SDHCI host to use the 'reset' callback to take the appropriate action (set flags, configure registers, etc) before the capabilities register(s) are read. Please note that some SDHCI hosts, such as the Tegra SDHCI host, has the ability to mask bits in the capabilities register to prevent certain capabilities from being advertised. Signed-off-by: Jon Hunter Acked-by: Adrian Hunter --- Although this is described as a "V2" this patch has been added since the original patch was posted. If the below is deemed not appropriate, then another solution I was thinking of is to allow the SDHCI host to call 'mmc_regulator_get_supply' before calling sdhci_setup_host() and then in sdhci_setup_host() check if any regulators are already present before calling mmc_regulator_get_supply(). drivers/mmc/host/sdhci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 2ee8bfa77116..628c4b3558c0 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3021,6 +3021,17 @@ int sdhci_setup_host(struct sdhci_host *host) mmc = host->mmc; + /* + * If there are external regulators, get them. Note + * this must be done early before resetting the host + * and reading the capabilities so that the host can + * take the appropriate action if regulators are not + * available. + */ + ret = mmc_regulator_get_supply(mmc); + if (ret == -EPROBE_DEFER) + return ret; + sdhci_read_caps(host); override_timeout_clk = host->timeout_clk; @@ -3253,11 +3264,6 @@ int sdhci_setup_host(struct sdhci_host *host) mmc_gpio_get_cd(host->mmc) < 0) mmc->caps |= MMC_CAP_NEEDS_POLL; - /* If there are external regulators, get them */ - ret = mmc_regulator_get_supply(mmc); - if (ret == -EPROBE_DEFER) - goto undma; - /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ if (!IS_ERR(mmc->supply.vqmmc)) { ret = regulator_enable(mmc->supply.vqmmc);