From patchwork Tue Jul 19 07:51:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Guojun X-Patchwork-Id: 9236267 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4E55C60574 for ; Tue, 19 Jul 2016 07:53:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4057720246 for ; Tue, 19 Jul 2016 07:53:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 349C32094F; Tue, 19 Jul 2016 07:53:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D620E205AA for ; Tue, 19 Jul 2016 07:53:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752976AbcGSHww (ORCPT ); Tue, 19 Jul 2016 03:52:52 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:40045 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752737AbcGSHwu (ORCPT ); Tue, 19 Jul 2016 03:52:50 -0400 Received: from 172.24.1.60 (EHLO szxeml422-hub.china.huawei.com) ([172.24.1.60]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id CFA02649; Tue, 19 Jul 2016 15:52:05 +0800 (CST) Received: from vm167-7.huawei.com (10.177.167.7) by szxeml422-hub.china.huawei.com (10.82.67.152) with Microsoft SMTP Server id 14.3.235.1; Tue, 19 Jul 2016 15:51:54 +0800 From: Jin Guojun To: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 1/2] Support SD UHS for hikey-mainline-rebase Date: Tue, 19 Jul 2016 15:51:52 +0800 Message-ID: <1468914713-63347-1-git-send-email-kid.jin@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.177.167.7] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.578DDC29.005C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6e76a767e368fc270666c4a206e98c0c Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: j00226943 Two more changes: Before we send cmd,we need to set CMD bit29 to 1 so that CMD and DATA sent to card through the HOLD Register, This is the explication in synosys host:To meet the relatively high Input Hold Time requirement for SDR12, SDR25, and other MMC speed modes, you should program bit[29]use_hold_Reg of the CMD register to 1'b1; the output data is then registered again in the cclk_in_drv domain by using the Hold Register as shown in Path B of Figure 10-8. However, for the higher speed modes of SDR104, SDR50 and DDR50, you can meet the much smaller Input Hold Time requirement of 0.8ns by bypassing the Hold Register (Path A in Figure 10-8, programming CMD.use_hold_reg = 1'b0) and then adding delay elements on the output path as indicated We have no tuning function in our drivers,so we must do the Function piling when we init UHS card. Signed-off-by: Jin Guojun --- drivers/mmc/host/dw_mmc-k3.c | 6 ++++++ drivers/mmc/host/dw_mmc.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c index 63c2e2e..2cbfcc7 100644 --- a/drivers/mmc/host/dw_mmc-k3.c +++ b/drivers/mmc/host/dw_mmc-k3.c @@ -125,10 +125,16 @@ static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios) host->bus_hz = clk_get_rate(host->biu_clk); } +static void dw_mci_hi6220_prepare_command(struct dw_mci *host, u32 *cmdr) +{ + *cmdr |= SDMMC_CMD_USE_HOLD_REG; +} + static const struct dw_mci_drv_data hi6220_data = { .switch_voltage = dw_mci_hi6220_switch_voltage, .set_ios = dw_mci_hi6220_set_ios, .parse_dt = dw_mci_hi6220_parse_dt, + .prepare_command = dw_mci_hi6220_prepare_command, }; static const struct of_device_id dw_mci_k3_match[] = { diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 9dd1bd3..047e116 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1564,6 +1564,8 @@ static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) if (drv_data && drv_data->execute_tuning) err = drv_data->execute_tuning(slot, opcode); + else + err = 0; return err; }