From patchwork Sat Jul 30 14:25:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 9253149 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4666E6077C for ; Sat, 30 Jul 2016 14:34:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 37535283EF for ; Sat, 30 Jul 2016 14:34:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2A8F428445; Sat, 30 Jul 2016 14:34:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D5C41283EF for ; Sat, 30 Jul 2016 14:34:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752138AbcG3O1d (ORCPT ); Sat, 30 Jul 2016 10:27:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50310 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751600AbcG3O0C (ORCPT ); Sat, 30 Jul 2016 10:26:02 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E7D268553E; Sat, 30 Jul 2016 14:26:01 +0000 (UTC) Received: from shalem.localdomain.com (vpn1-5-7.ams2.redhat.com [10.36.5.7]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u6UEPo42005750; Sat, 30 Jul 2016 10:25:59 -0400 From: Hans de Goede To: Ulf Hansson , Maxime Ripard , Chen-Yu Tsai Cc: linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree , Icenowy Zheng , Hans de Goede Subject: [PATCH v2 3/5] mmc: sunxi: Factor out clock phase setting code into a helper function Date: Sat, 30 Jul 2016 16:25:46 +0200 Message-Id: <1469888748-26085-4-git-send-email-hdegoede@redhat.com> In-Reply-To: <1469888748-26085-1-git-send-email-hdegoede@redhat.com> References: <1469888748-26085-1-git-send-email-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Sat, 30 Jul 2016 14:26:02 +0000 (UTC) Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a sunxi_mmc_clk_set_phase() helper function. Signed-off-by: Hans de Goede Acked-by: Maxime Ripard --- Changes in v2: -New patch in v2 of this patch-set --- drivers/mmc/host/sunxi-mmc.c | 61 ++++++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 9f44c83..b631b5c 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -657,12 +657,39 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) return 0; } +static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, + struct mmc_ios *ios, u32 rate) +{ + int index; + + /* determine delays */ + if (rate <= 400000) { + index = SDXC_CLK_400K; + } else if (rate <= 25000000) { + index = SDXC_CLK_25M; + } else if (rate <= 52000000) { + if (ios->timing != MMC_TIMING_UHS_DDR50 && + ios->timing != MMC_TIMING_MMC_DDR52) { + index = SDXC_CLK_50M; + } else if (ios->bus_width == MMC_BUS_WIDTH_8) { + index = SDXC_CLK_50M_DDR_8BIT; + } else { + index = SDXC_CLK_50M_DDR; + } + } else { + return -EINVAL; + } + + clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); + clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); + + return 0; +} + static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, struct mmc_ios *ios) { - const struct sunxi_mmc_clk_delay *clk_delays = host->cfg->clk_delays; - u32 rate, oclk_dly, rval, sclk_dly; - u32 clock = ios->clock; + u32 rate, rval, clock = ios->clock; int ret; /* 8 bit DDR requires a higher module clock */ @@ -697,31 +724,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, } mmc_writel(host, REG_CLKCR, rval); - /* determine delays */ - if (rate <= 400000) { - oclk_dly = clk_delays[SDXC_CLK_400K].output; - sclk_dly = clk_delays[SDXC_CLK_400K].sample; - } else if (rate <= 25000000) { - oclk_dly = clk_delays[SDXC_CLK_25M].output; - sclk_dly = clk_delays[SDXC_CLK_25M].sample; - } else if (rate <= 52000000) { - if (ios->timing != MMC_TIMING_UHS_DDR50 && - ios->timing != MMC_TIMING_MMC_DDR52) { - oclk_dly = clk_delays[SDXC_CLK_50M].output; - sclk_dly = clk_delays[SDXC_CLK_50M].sample; - } else if (ios->bus_width == MMC_BUS_WIDTH_8) { - oclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].output; - sclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].sample; - } else { - oclk_dly = clk_delays[SDXC_CLK_50M_DDR].output; - sclk_dly = clk_delays[SDXC_CLK_50M_DDR].sample; - } - } else { - return -EINVAL; - } - - clk_set_phase(host->clk_sample, sclk_dly); - clk_set_phase(host->clk_output, oclk_dly); + ret = sunxi_mmc_clk_set_phase(host, ios, rate); + if (ret) + return ret; return sunxi_mmc_oclk_onoff(host, 1); }