From patchwork Wed Aug 24 10:03:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9297361 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 047AA607D0 for ; Wed, 24 Aug 2016 10:05:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EAAC128EDE for ; Wed, 24 Aug 2016 10:05:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DF6A428EE4; Wed, 24 Aug 2016 10:05:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED95128EDE for ; Wed, 24 Aug 2016 10:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754925AbcHXKFi (ORCPT ); Wed, 24 Aug 2016 06:05:38 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:34273 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753920AbcHXKFd (ORCPT ); Wed, 24 Aug 2016 06:05:33 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5158261D67; Wed, 24 Aug 2016 10:04:52 +0000 (UTC) Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 50B1D61BD3; Wed, 24 Aug 2016 10:04:45 +0000 (UTC) From: Ritesh Harjani To: adrian.hunter@intel.com Cc: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, pramod.gurav@linaro.org, bjorn.andersson@linaro.org, Ritesh Harjani Subject: [PATCH v4 8/9] mmc: sdhci-msm: Add clock changes for DDR mode. Date: Wed, 24 Aug 2016 15:33:43 +0530 Message-Id: <1472033024-14890-9-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1472033024-14890-1-git-send-email-riteshh@codeaurora.org> References: <1472033024-14890-1-git-send-email-riteshh@codeaurora.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by: Ritesh Harjani --- drivers/mmc/host/sdhci-msm.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 853639b..538594c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -667,21 +667,35 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); - u32 msm_clock = 0; + struct mmc_ios curr_ios = host->mmc->ios; + u32 msm_clock, ddr_clock; int rc = 0; if (!clock) goto out; - if (clock != msm_host->clk_rate) { - msm_clock = sdhci_msm_get_msm_clk_rate(host, clock); + msm_clock = sdhci_msm_get_msm_clk_rate(host, clock); + if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || + (curr_ios.timing == MMC_TIMING_MMC_HS400)) { + /* + * The SDHC requires internal clock frequency to be double the + * actual clock that will be set for DDR mode. The controller + * uses the faster clock(100/400MHz) for some of its parts and + * send the actual required clock (50/200MHz) to the card. + */ + ddr_clock = clock * 2; + msm_clock = sdhci_msm_get_msm_clk_rate(host, ddr_clock); + } + + if (msm_clock != msm_host->clk_rate) { rc = clk_set_rate(msm_host->clk, msm_clock); if (rc) { pr_err("%s: failed to set clock at rate %u, requested clock rate %u\n", mmc_hostname(host->mmc), msm_clock, clock); goto out; } - msm_host->clk_rate = clock; + msm_host->clk_rate = msm_clock; pr_debug("%s: setting clock at rate %lu\n", mmc_hostname(host->mmc), clk_get_rate(msm_host->clk)); }