From patchwork Wed Oct 5 14:40:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9363035 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C10C76075E for ; Wed, 5 Oct 2016 14:42:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B1E3F28957 for ; Wed, 5 Oct 2016 14:42:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6B1728979; Wed, 5 Oct 2016 14:42:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4009B28994 for ; Wed, 5 Oct 2016 14:42:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754546AbcJEOmE (ORCPT ); Wed, 5 Oct 2016 10:42:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50045 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754407AbcJEOmD (ORCPT ); Wed, 5 Oct 2016 10:42:03 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 95940618B2; Wed, 5 Oct 2016 14:42:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475678522; bh=6QTkM8Qx6pxP/W7n2un1OQYUPwer99q/63EzAsPA0hQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=esueeX4/TWHnIFSHIOW874KMjLuQUlqGwEMo5J1HbNyIS+5U3K5GQ1uhvnhtz/HkP 74OFBdYvaWDD3/QchQ/1o6fvQOrO4rcYKwkRIELNodWng9UuvNBYwp0tAWNY+fUyCU kz4f8NG1IKdZ38FHqj+x6TWD9L4W25c1EU3GiMhc= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 275DA616DC; Wed, 5 Oct 2016 14:41:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475678521; bh=6QTkM8Qx6pxP/W7n2un1OQYUPwer99q/63EzAsPA0hQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=APg3MDD1+DmpS3qNIrSuf+Tj4B2UZ52/Srz0IWuGVJtdAyNMolqwySKUTyu94xG/4 I2PgjS8/mUM+wJG3kppyzN5zicTkhkiglzzWr04WeKRB6/DvTcvdOgJ6EMnEMEC0H6 BxyqxDcYrlnF0gtqzT68vaqy1D6lGc8tVbJXP4xM= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 275DA616DC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, shawn.lin@rock-chips.com Cc: david.brown@linaro.org, andy.gross@linaro.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, sboyd@codeaurora.org, bjorn.andersson@linaro.org, pramod.gurav@linaro.org, Ritesh Harjani Subject: [PATCH v5 07/12] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Date: Wed, 5 Oct 2016 20:10:35 +0530 Message-Id: <1475678440-3525-8-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1475678440-3525-1-git-send-email-riteshh@codeaurora.org> References: <1475678440-3525-1-git-send-email-riteshh@codeaurora.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP sdhci-msm controller may have different clk-rates for each bus speed mode. Thus implement set_clock callback for sdhci-msm driver. Signed-off-by: Sahitya Tummala Signed-off-by: Ritesh Harjani --- drivers/mmc/host/sdhci-msm.c | 110 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 109 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 542ddad..9d18cf0 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -84,6 +84,7 @@ struct sdhci_msm_host { struct clk *bus_clk; /* SDHC bus voter clock */ u32 *clk_table; int clk_table_sz; + u32 clk_rate; struct mmc_host *mmc; bool use_14lpp_dll_reset; }; @@ -588,6 +589,113 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) } } +static unsigned int sdhci_msm_get_msm_clk_rate(struct sdhci_host *host, + u32 req_clk) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + int count; + unsigned int sel_clk = -1; + + if (!msm_host->clk_table) + return clk_round_rate(msm_host->clk, ULONG_MAX); + + count = msm_host->clk_table_sz; + + while (count--) { + sel_clk = msm_host->clk_table[count]; + if (req_clk >= sel_clk) + return sel_clk; + } + + return sel_clk; +} + +/** + * __sdhci_msm_set_clock - sdhci_msm clock control. + * + * Description: + * Implement MSM version of sdhci_set_clock. + * This is required since MSM controller does not + * use internal divider and instead directly control + * the GCC clock as per HW recommendation. + **/ +void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) +{ + u16 clk; + unsigned long timeout; + + /* + * Keep actual_clock as zero - + * - since there is no divider used so no need of having actual_clock. + * - MSM controller uses SDCLK for data timeout calculation. If + * actual_clock is zero, host->clock is taken for calculation. + */ + host->mmc->actual_clock = 0; + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return; + + /* + * MSM controller do not use clock divider. + * Thus read SDHCI_CLOCK_CONTROL and only enable + * clock with no divider value programmed. + */ + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk |= SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 20 ms */ + timeout = 20; + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + return; + } + timeout--; + mdelay(1); + } + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +} + +static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + u32 msm_clock; + int rc; + + if (!clock) + goto out; + + spin_unlock_irq(&host->lock); + if ((clock != msm_host->clk_rate) && msm_host->clk_table) { + msm_clock = sdhci_msm_get_msm_clk_rate(host, clock); + rc = clk_set_rate(msm_host->clk, msm_clock); + if (rc) { + pr_err("%s: failed to set clock at rate %u, requested clock rate %u\n", + mmc_hostname(host->mmc), msm_clock, clock); + goto out; + } + msm_host->clk_rate = clock; + pr_debug("%s: setting clock at rate %lu\n", + mmc_hostname(host->mmc), clk_get_rate(msm_host->clk)); + } + + spin_lock_irq(&host->lock); +out: + if (!msm_host->clk_table) + return sdhci_set_clock(host, clock); + __sdhci_msm_set_clock(host, clock); +} + static const struct of_device_id sdhci_msm_dt_match[] = { { .compatible = "qcom,sdhci-msm-v4" }, {}, @@ -598,7 +706,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); static const struct sdhci_ops sdhci_msm_ops = { .platform_execute_tuning = sdhci_msm_execute_tuning, .reset = sdhci_reset, - .set_clock = sdhci_set_clock, + .set_clock = sdhci_msm_set_clock, .get_min_clock = sdhci_msm_get_min_clock, .get_max_clock = sdhci_msm_get_max_clock, .set_bus_width = sdhci_set_bus_width,