From patchwork Wed Oct 5 14:40:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9363039 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 364D46075E for ; Wed, 5 Oct 2016 14:42:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2897B28957 for ; Wed, 5 Oct 2016 14:42:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1D27C28994; Wed, 5 Oct 2016 14:42:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AD99028979 for ; Wed, 5 Oct 2016 14:42:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754164AbcJEOmL (ORCPT ); Wed, 5 Oct 2016 10:42:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50118 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753781AbcJEOmK (ORCPT ); Wed, 5 Oct 2016 10:42:10 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D6B1261599; Wed, 5 Oct 2016 14:42:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475678529; bh=VoEzoPVLmxtZ56pMTMVou/6TnbX0glfReGbzBbiuXHE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EJWJIPYPUe5i2hCgAU6/YOd/DUyRM0KA21W86e7lnB4QwQUWzyjyUCBKB9qW1Huse s+2ENI2K7+4Nz4NZY9Y7v06D8++g2G+PizQRSisV8VR1/i1cELPw99doFUYq9Aj1sL gir9GJGGEZL8gR6FEQk7vXhupmSeN6dOCoEkSWtM= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3F9A461A06; Wed, 5 Oct 2016 14:42:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475678528; bh=VoEzoPVLmxtZ56pMTMVou/6TnbX0glfReGbzBbiuXHE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D8JAK+etZ9P6wRS/KnEnqB5rBP4jqVWNj+PxnxIauxdNDtG/0V5aP5JPFb3NKrbax 6S7cVWagh+XXKv44QMlx2TCH2GKI4UQx0OqGyoTdOVSVgny+5ls7sWaawbxNvsqsq3 AArTypX+ckpy6v3v2O/Q5qZI4sNujJH7NoWwEAkU= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 3F9A461A06 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, shawn.lin@rock-chips.com Cc: david.brown@linaro.org, andy.gross@linaro.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, sboyd@codeaurora.org, bjorn.andersson@linaro.org, pramod.gurav@linaro.org, Ritesh Harjani Subject: [PATCH v5 08/12] mmc: sdhci-msm: Add clock changes for DDR mode. Date: Wed, 5 Oct 2016 20:10:36 +0530 Message-Id: <1475678440-3525-9-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1475678440-3525-1-git-send-email-riteshh@codeaurora.org> References: <1475678440-3525-1-git-send-email-riteshh@codeaurora.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by: Ritesh Harjani Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 9d18cf0..eb1a9e3 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -669,6 +669,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + struct mmc_ios curr_ios = host->mmc->ios; u32 msm_clock; int rc; @@ -676,15 +677,29 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) goto out; spin_unlock_irq(&host->lock); - if ((clock != msm_host->clk_rate) && msm_host->clk_table) { - msm_clock = sdhci_msm_get_msm_clk_rate(host, clock); + if (((curr_ios.timing == MMC_TIMING_UHS_DDR50) || + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || + (curr_ios.timing == MMC_TIMING_MMC_HS400)) && + msm_host->clk_table) { + /* + * The SDHC requires internal clock frequency to be double the + * actual clock that will be set for DDR mode. The controller + * uses the faster clock(100/400MHz) for some of its parts and + * send the actual required clock (50/200MHz) to the card. + */ + clock *= 2; + } + msm_clock = sdhci_msm_get_msm_clk_rate(host, clock); + + if ((msm_clock != msm_host->clk_rate) && msm_host->clk_table) { rc = clk_set_rate(msm_host->clk, msm_clock); if (rc) { - pr_err("%s: failed to set clock at rate %u, requested clock rate %u\n", - mmc_hostname(host->mmc), msm_clock, clock); + pr_err("%s: failed to set clock at rate %u at timing %d\n", + mmc_hostname(host->mmc), msm_clock, + curr_ios.timing); goto out; } - msm_host->clk_rate = clock; + msm_host->clk_rate = msm_clock; pr_debug("%s: setting clock at rate %lu\n", mmc_hostname(host->mmc), clk_get_rate(msm_host->clk)); }